Papers on COINS

1. Sassa, M., Nakaya, T., Kohama, M., Fukuoka, T. and Takahashi, M.:
   Static Single Assignment Form in the COINS Compiler Infrastructure,
   SSGRR 2003w - International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, e-Medicine, and Mobile Technologies on the Internet, L'Aquila, Italy, No. 54 (Jan. 2003).
2. Sassa, M., Nakaya, T., Kohama, M., Fukuoka, T., Takahashi, M. and Nakata, I.:
   Static Single Assignment Form in the COINS Compiler Infrastructure - Current Status and Background -,
   Proc. of JSSST Workshop on Programming and Application Systems (SPA2003) (Mar. 2003).
   http://spa.jssst.or.jp/2003/program/papers/03006.pdf
3. Iwasawa, K., Kusaba, T.:
   Loop Shift Conversion for a Parallelizing Compiler,
   Proceedings of the 21st IASTED International Conference PDCN (Parallel and Distributed Computing and Network), pp.472-477 (Feb. 2003).
4. Sassa, M., Kohama, M. and Ito, Y.:
   Comparison and Evaluation of Back Translation Algorithms for Static Single Assignment Form,
   in Proc. IPSI-2004 Prague, Czech, ISBN: 86-7466-117-3 (Dec. 2004).
5. Mitsugu Suzuki, Nobuhisa Fujinami, Takeaki Fukuoka, Tan Watanabe, Ikuo Nakata:
   SIMD Optimization in COINS Compiler Infrastructure,
   Post Proc. 8th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA2005), pp.131-140 (Jan. 2005).
6. Saitou, T., Suzuki, M. and Watanabe, T.:
   Dominance Analysis of Irreducible CFGs by Reduction,
   ACM SIGPLAN Notices, Vol.40, No.4, pp.19-19 (Apr. 2005)
7. Abe, S., Hagiya, M. and Nakata, I.:
   A Retargetable Code Generator for the Generic Intermediate Language in COINS,
   IPSJ Journal: Programming, Vol.46, No.SIG 14 (PRO 27), pp. 12-29 (Oct. 2005).
8. Masataka Sassa, Yo Ito, and Masaki Kohama:
   Comparison and Evaluation of Back-translation Algorithms for Static Single Assignment Forms,
   Research Report C-214, Dept. of Mathematical and Computing Sciences, Tokyo Institute of Technology (Oct. 2005)
   http://www.is.titech.ac.jp/research/research-report/C/C-214.pdf
9. Masataka Sassa and Daijiro Sudo:
   Experience in Testing Compiler Optimizers Using Comparison Checking
   Research Report C-221, Dept. of Mathematical and Computing Sciences, Tokyo Institute of Technology (Feb. 2006)
   http://www.is.titech.ac.jp/research/research-report/C/C-221.pdf
10. Sassa, M. and Sudo. D.:
    Experience in Testing Compiler Optimizers Using Comparison Checking,
    2006 International Conference on Programming Languages and Compilers (PLC '06), Vol. II, pp. 837-843, CSREA Press (Jun. 2006).
11. Tan Watanabe, Tetsuro Fujise, Koichiro Mori, Kyoko Iwasawa, Ikuo Nakata:
    Design assists for embedded systems in the COINS Compiler Infrastructure,
    10th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA2007) Post proceedings, pp. 66-69 (Jan. 2007).
12. IwasawaCK., Mycroft, A.:
    Choosing Method of the Most Effective Nested Loop Shearing for Parallelism,
    Proceedings of Eighth International Conference on Parallel and Dostributed Computing, Applications and Technologies(PDCAT 2007), pp.267-276 (Dec. 2007).
13. Sassa, M. and Sahara, S.:
    Validating Correctness of Compiler Optimizer Execution Using Temporal Logic,
    Seventh International Workshop on Compiler Optimization meets Compiler Verification (COCV 2008) pp. 1-17 (April 2008).