;;;;
;;;; Target Description File
;;;; Sparc V9 architecture
;;;;

;;;
;;; Addressing mode symbols
;;;
;;;	<freg>
;;;	  freg (Floating-pointレジスタ)
;;;
;;;	<reg>
;;;	  reg (Integerレジスタ)
;;;
;;;	<dreg>
;;;	  dreg (Integerレジスタ対(64bit))
;;;
;;;	<address>
;;;	  reg
;;;	  reg + reg
;;;	  reg + imm13
;;;	  imm13
;;;
;;;	<regaddr> ("register-only address")
;;;	*** regaddrは Alternate Address Space命令のみのため未サポート ***
;;;	  reg
;;;	  reg + reg
;;;
;;;	<imm22> (sethiのみ)
;;;	  imm22
;;;
;;;	<imm32>
;;;	  imm32
;;;
;;;	<reg_or_imm> ("register or immediate value")
;;;	  reg
;;;	  imm13
;;;
;;;	<software_trap#>
;;;	*** TRAPは未サポート ***
;;;	  reg
;;;	  reg + reg
;;;	  reg + imm7
;;;	  uimm7
;;;
;;;	<label>
;;;	  label
;;;
;;;  中間言語でのHOLE表現は以下の通り
;;;    <freg> "F"マクロ・テンプレート
;;;     freg      ⇒ ?ng	下位32ビット
;;;     freg      ⇒ ?nG	上位32ビット
;;;     freg      ⇒ ?nf	64ビット
;;;    <reg>
;;;     reg       ⇒ ?nr
;;;    <dreg>
;;;     dreg      ⇒ ?nd
;;;    <address> "A"マクロ・テンプレート
;;;     reg       ⇒ ?nr
;;;     reg+reg   ⇒ ?nr+?nr
;;;     reg+imm13 ⇒ ?nr+?ni
;;;     reg+imm13 ⇒ ?nr+%lo(?na)
;;;     imm13     ⇒ ?ni
;;;     imm13     ⇒ %lo(?na)
;;;    <reg_or_imm> "R"マクロ・テンプレート
;;;     reg       ⇒ ?nr
;;;     imm13     ⇒ ?ni
;;;     imm13     ⇒ %lo(?na)
;;;    <imm22> (sethiのみ)
;;;     imm22     ⇒ ?nh
;;;    <imm32> (%hi、%loを使う場合)
;;;     imm32     ⇒ ?nI
;;;    <label>
;;;     label     ⇒ ?nl (LABEL CELL)
;;;	label     ⇒ ?na (ASMCONST CELL)
;;;    <reg_or_imm> "S"マクロ・テンプレート(シフト命令のビット・カウント)
;;;     reg       ⇒ ?nr (CONVIT I5 (REG I32 xxx))
;;;     imm5      ⇒ ?ni (INTCONST I5 xxxx)
;;;    <reg_or_imm6> "T"マクロ・テンプレート(シフト命令のビット・カウント)
;;;     reg       ⇒ ?nr (CONVIT I6 (REG I64 xxx))
;;;     imm6      ⇒ ?ni (INTCONST I6 xxxx)
;;;    <reg_or_imm10> "U"マクロ・テンプレート
;;;     reg       ⇒ ?nr
;;;     imm10     ⇒ ?ni
;;;    <reg_or_imm11> "V"マクロ・テンプレート
;;;     reg       ⇒ ?nr
;;;     imm11     ⇒ ?ni


;;;
;;; アセンブラ定義
;;;
(DEFLANG SOLARIS GAS)

;;;
;;; 記号定義
;;;
(DEFNAME IREG				; 64bit整数レジスタ
  (g0 g1 g2 g3 g4 g5 g6 g7
      o0 o1 o2 o3 o4 o5 o6 o7
      l0 l1 l2 l3 l4 l5 l6 l7
      i0 i1 i2 i3 i4 i5 i6 i7))

(DEFNAME IREG_D				; 64bit整数レジスタ
  (g1 g2 g3 g4 g5 g6 g7			; destination operand
      o0 o1 o2 o3 o4 o5 o6 o7
      l0 l1 l2 l3 l4 l5 l6 l7
      i0 i1 i2 i3 i4 i5 i6 i7))

(DEFNAME FREG				; 64bit浮動小数点レジスタ
  (f0 f2 f4 f6 f8 f10 f12 f14
      f16 f18 f20 f22 f24 f26 f28 f30
      f32 f34 f36 f38 f40 f42 f44 f46
      f48 f50 f52 f54 f56 f58 f60 f62))

(DEFNAME FREG_S				; 64/32bit浮動小数点レジスタ
  (f0 f2 f4 f6 f8 f10 f12 f14
      f16 f18 f20 f22 f24 f26 f28 f30))

;;;----------------------------------------------------------------------
;;;
;;; Add
;;;
;;;	ADD	Add
;;;	ADDcc	Add and modify cc's
;;;	ADDC	Add with Carry
;;;	ADDCcc	Add with Carry and modify cc's
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Add ==
;; add reg, reg_or_imm, reg
(DEFINST ("add ?1r, ??2R, ?3r" "add ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Add and modify cc's ==
;; addcc reg, reg_or_imm, reg
(DEFINST ("addcc ?1r, ??2R, ?3r" "addcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (CONVIT I32 (HOLE 2)) (INTCONST I1 0)))
   (SET (REG I1 icc_c)
	(CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		(CONVIT I32 (HOLE 2)) (INTCONST I1 0)))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   (SET (REG I1 xcc_c)
	(CARRY  I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   )
  )

;; destinationがg0の場合はフラグのみ設定する
(DEFINST ("addcc ?1r, ??2R, %g0" "addcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (CONVIT I32 (HOLE 2)) (INTCONST I1 0)))
   (SET (REG I1 icc_c)
	(CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		(CONVIT I32 (HOLE 2)) (INTCONST I1 0)))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
		(INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   (SET (REG I1 xcc_c)
	(CARRY  I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   )
  )

;; == Add with Carry ==
;; addc reg, reg_or_imm, reg
(DEFINST ("addc ?1r, ??2R, ?3r" "addc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(ADD I64 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	     (CONVZX I64 (REG I1 icc_c))))
   )
  )

;; == Add with Carry and modify cc's ==
;; addccc reg, reg_or_imm, reg
(DEFINST ("addccc ?1r, ??2R, ?3r" "addccc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(ADD I64 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	     (CONVZX I64 (REG I1 icc_c))))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
		(CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (CONVIT I32 (HOLE 2)) (REG I1 icc_c)))
   (SET (REG I1 icc_c)
	(CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		(CONVIT I32 (HOLE 2)) (REG I1 icc_c)))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (ADD I64 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
			(CONVZX I64 (REG I1 icc_c)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (ADD I64 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
		       (CONVZX I64 (REG I1 icc_c)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (REG I1 icc_c)))
   (SET (REG I1 xcc_c)
	(CARRY  I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (REG I1 icc_c)))
   )
  )

;; destinationがg0の場合はフラグのみ設定する
(DEFINST ("addccc ?1r, ??2R, %g0" "addccc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
		(CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (CONVIT I32 (HOLE 2)) (REG I1 icc_c)))
   (SET (REG I1 icc_c)
	(CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		(CONVIT I32 (HOLE 2)) (REG I1 icc_c)))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (ADD I64 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
			(CONVZX I64 (REG I1 icc_c)))
		(INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (ADD I64 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
		       (CONVZX I64 (REG I1 icc_c)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (REG I1 icc_c)))
   (SET (REG I1 xcc_c)
	(CARRY  I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (REG I1 icc_c)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Branch on Integer Register with Prediction (BPr)
;;;
;;;	BRZ	Branch on Register Zero
;;;	BRLEZ	Branch on Register Less Than or Equal to Zero
;;;	BRLZ	Branch on Register Less Than Zero
;;;	BRNZ	Branch on Register Not Zero
;;;	BRGZ	Branch on Register Greater Than Zero
;;;	BRGEZ	Branch on Register Greater Than or Equal to Zero
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Branch on Register Zero ==
;; brz{,a}{,pt|,pn} reg, label
(DEFINST ("brz ?1r, ?2l" "brz ?1r, ?2l")
  (PARALLEL
   (DELAYEDJUMPC
    (TSTEQ I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("brz,a ?1r, ?2l" "brz,a ?1r, ?2l")
  (PARALLEL
   (ANNULEDJUMPC
    (TSTEQ I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Register Less Than or Equal to Zero ==
;; brlez{,a}{,pt|,pn} reg, label
(DEFINST ("brlez ?1r, ?2l" "brlez ?1r, ?2l")
  (PARALLEL
   (DELAYEDJUMPC
    (TSTLES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("brlez,a ?1r, ?2l" "brlez,a ?1r, ?2l")
  (PARALLEL
   (ANNULEDJUMPC
    (TSTLES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Register Less Than Zero ==
;; brlz{,a}{,pt|,pn} reg, label
(DEFINST ("brlz ?1r, ?2l" "brlz ?1r, ?2l")
  (PARALLEL
   (DELAYEDJUMPC
    (TSTLTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("brlz,a ?1r, ?2l" "brlz,a ?1r, ?2l")
  (PARALLEL
   (ANNULEDJUMPC
    (TSTLTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Register Not Zero ==
;; brnz{,a}{,pt|,pn} reg, label
(DEFINST ("brnz ?1r, ?2l" "brnz ?1r, ?2l")
  (PARALLEL
   (DELAYEDJUMPC
    (TSTNE I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("brnz,a ?1r, ?2l" "brnz,a ?1r, ?2l")
  (PARALLEL
   (ANNULEDJUMPC
    (TSTNE I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Register Greater Than Zero ==
;; brgz{,a}{,pt|,pn} reg, label
(DEFINST ("brgz ?1r, ?2l" "brgz ?1r, ?2l")
  (PARALLEL
   (DELAYEDJUMPC
    (TSTGTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("brgz,a ?1r, ?2l" "brgz,a ?1r, ?2l")
  (PARALLEL
   (ANNULEDJUMPC
    (TSTGTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Register Greater Than or Equal to Zero ==
;; brgez{,a}{,pt|,pn} reg, label
(DEFINST ("brgez ?1r, ?2l" "brgez ?1r, ?2l")
  (PARALLEL
   (DELAYEDJUMPC
    (TSTGES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("brgez,a ?1r, ?2l" "brgez,a ?1r, ?2l")
  (PARALLEL
   (ANNULEDJUMPC
    (TSTGES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
    (LABEL I64 (HOLE 2)))
   )
  )

;;;----------------------------------------------------------------------
;;;
;;; Branch on Floating-Point Condition Codes (FBfcc)
;;;
;;; *** Deprecated ***
;;;
;;;	FBA	Branch Always
;;;	FBN	Branch Never
;;;	FBU	Branch on Unordered
;;;	FBG	Branch on Greater
;;;	FBUG	Branch on Unordered or Greater
;;;	FBL	Branch on Less
;;;	FBUL	Branch on Unordered or Less
;;;	FBLG	Branch on Less or Greater
;;;	FBNE	Branch on Not Equal
;;;	FBE	Branch on Equal
;;;	FBUE	Branch on Unordered or Equal
;;;	FBGE	Branch on Greater or Equal
;;;	FBUGE	Branch on Unordered or Greater or Equal
;;;	FBLE	Branch on Less or Equal
;;;	FBULE	Branch on Unordered or Less or Equal
;;;	FBO	Branch on Ordered
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Branch Always ==
;; fba label
(DEFINST ("fba ?1l" "fba ?1l")
  (PARALLEL
   (DELAYEDJUMP (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fba,a ?1l" "fba,a ?1l")
  (PARALLEL
   (JUMP (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch Never ==
;; fbn label
;;(DEFINST ("fbn ?1l" "fbn ?1l")
;;  (PARALLEL
;;   )
;;  )

(DEFINST ("fbn,a ?1l" "fbn,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (INTCONST I1 0) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Unordered ==
;; fbu label
(DEFINST ("fbu ?1l" "fbu ?1l")
  (PARALLEL
   (DELAYEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))  (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbu,a ?1l" "fbu,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))  (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater ==
;; fbg label
(DEFINST ("fbg ?1l" "fbg ?1l")
  (PARALLEL
   (DELAYEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2))  (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbg,a ?1l" "fbg,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2))  (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Unordered or Greater ==
;; fbug label
(DEFINST ("fbug ?1l" "fbug ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbug,a ?1l" "fbug,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Less ==
;; fbl label
(DEFINST ("fbl ?1l" "fbl ?1l")
  (PARALLEL
   (DELAYEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1))  (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbl,a ?1l" "fbl,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1))  (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Unordered or Less ==
;; fbul label
(DEFINST ("fbul ?1l" "fbul ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbul,a ?1l" "fbul,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Less or Greater ==
;; fblg label
(DEFINST ("fblg ?1l" "fblg ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fblg,a ?1l" "fblg,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Not Equal ==
;; *** fbnzと同一のため定義しない ***
;; fbne label
;;(DEFINST ("fbne ?1l" "fbne ?1l")
;;  (PARALLEL
;;   (DELAYEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 0))
;;                 (LABEL I64 (HOLE 1)))
;;   )
;;  )

;;(DEFINST ("fbne,a ?1l" "fbne,a ?1l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 0))
;;                 (LABEL I64 (HOLE 1)))
;;   )
;;  )

;; == Branch on Equal ==
;; *** fbzと同一のため定義しない ***
;; fbe label
;;(DEFINST ("fbe ?1l" "fbe ?1l")
;;  (PARALLEL
;;   (DELAYEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0))
;;                 (LABEL I64 (HOLE 1)))
;;   )
;;  )

;;(DEFINST ("fbe,a ?1l" "fbe,a ?1l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0))
;;                 (LABEL I64 (HOLE 1)))
;;   )
;;  )

;; == Branch on Unordered or Equal ==
;; fbue label
(DEFINST ("fbue ?1l" "fbue ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbue,a ?1l" "fbue,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 3))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater or Equal ==
;; fbge label
(DEFINST ("fbge ?1l" "fbge ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbge,a ?1l" "fbge,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 2))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Unordered or Greater or Equal ==
;; fbuge label
(DEFINST ("fbuge ?1l" "fbuge ?1l")
  (PARALLEL
   (DELAYEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 1))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbuge,a ?1l" "fbuge,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 1))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Less or Equal ==
;; fble label
(DEFINST ("fble ?1l" "fble ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fble,a ?1l" "fble,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (REG I2 fcc) (INTCONST I2 1))
		      (TSTEQ I1 (REG I2 fcc) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Unordered or Less or Equal ==
;; fbule label
(DEFINST ("fbule ?1l" "fbule ?1l")
  (PARALLEL
   (DELAYEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 2))  (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbule,a ?1l" "fbule,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 2))  (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Ordered ==
;; fbo label
(DEFINST ("fbo ?1l" "fbo ?1l")
  (PARALLEL
   (DELAYEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 3)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("fbo,a ?1l" "fbo,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (TSTNE I1 (REG I2 fcc) (INTCONST I2 3)) (LABEL I64 (HOLE 1)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Branch on Floating-Point Condition Codes with Prediction (FBPfcc)
;;;
;;;	FBPA	Branch Always
;;;	FBPN	Branch Never
;;;	FBPU	Branch on Unordered
;;;	FBPG	Branch on Greater
;;;	FBPUG	Branch on Unordered or Greater
;;;	FBPL	Branch on Less
;;;	FBPUL	Branch on Unordered or Less
;;;	FBPLG	Branch on Less or Greater
;;;	FBPNE	Branch on Not Equal
;;;	FBPE	Branch on Equal
;;;	FBPUE	Branch on Unordered or Equal
;;;	FBPGE	Branch on Greater or Equal
;;;	FBPUGE	Branch on Unordered or Greater or Equal
;;;	FBPLE	Branch on Less or Equal
;;;	FBPULE	Branch on Unordered or Less or Equal
;;;	FBPO	Branch on Ordered
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Branch Always ==
;; fba label
(DEFINST ("fba ??1D, ?2l" "fba ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMP (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fba,a ??1D, ?2l" "fba,a ??1D, ?2l")
  (PARALLEL
   (JUMP (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch Never ==
;; fbn label
;;(DEFINST ("fbn ??1D, ?2l" "fbn ??1D, ?2l")
;;  (PARALLEL
;;   )
;;  )

(DEFINST ("fbn,a ??1D, ?2l" "fbn,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (INTCONST I1 0) (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Unordered ==
;; fbu label
(DEFINST ("fbu ??1D, ?2l" "fbu ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 3))  (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbu,a ??1D, ?2l" "fbu,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 3))  (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Greater ==
;; fbg label
(DEFINST ("fbg ??1D, ?2l" "fbg ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 2))  (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbg,a ??1D, ?2l" "fbg,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 2))  (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Unordered or Greater ==
;; fbug label
(DEFINST ("fbug ??1D, ?2l" "fbug ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbug,a ??1D, ?2l" "fbug,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Less ==
;; fbl label
(DEFINST ("fbl ??1D, ?2l" "fbl ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 1))  (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbl,a ??1D, ?2l" "fbl,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 1))  (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Unordered or Less ==
;; fbul label
(DEFINST ("fbul ??1D, ?2l" "fbul ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 1)))
		 (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbul,a ??1D, ?2l" "fbul,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 1)))
		 (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Less or Greater ==
;; fblg label
(DEFINST ("fblg ??1D, ?2l" "fblg ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fblg,a ??1D, ?2l" "fblg,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		 (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Not Equal ==
;; *** fbnzと同一のため定義しない ***
;; fbne label
;;(DEFINST ("fbne ??1D, ?2l" "fbne ??1D, ?2l")
;;  (PARALLEL
;;   (DELAYEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 0))  (LABEL I64 (HOLE 2)))
;;   )
;;  )

;;(DEFINST ("fbne,a ??1D, ?2l" "fbne,a ??1D, ?2l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 0))  (LABEL I64 (HOLE 2)))
;;   )
;;  )

;; == Branch on Equal ==
;; *** fbzと同一のため定義しない ***
;; fbe label
;;(DEFINST ("fbe ??1D, ?2l" "fbe ??1D, ?2l")
;;  (PARALLEL
;;   (DELAYEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 0))  (LABEL I64 (HOLE 2)))
;;   )
;;  )

;;(DEFINST ("fbe,a ??1D, ?2l" "fbe,a ??1D, ?2l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (TSTEQ I1 (HOLE 1) (INTCONST I2 0))  (LABEL I64 (HOLE 2)))
;;   )
;;  )

;; == Branch on Unordered or Equal ==
;; fbue label
(DEFINST ("fbue ??1D, ?2l" "fbue ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbue,a ??1D, ?2l" "fbue,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Greater or Equal ==
;; fbge label
(DEFINST ("fbge ??1D, ?2l" "fbge ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbge,a ??1D, ?2l" "fbge,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Unordered or Greater or Equal ==
;; fbuge label
(DEFINST ("fbuge ??1D, ?2l" "fbuge ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 1))  (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbuge,a ??1D, ?2l" "fbuge,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 1))  (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Less or Equal ==
;; fble label
(DEFINST ("fble ??1D, ?2l" "fble ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fble,a ??1D, ?2l" "fble,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
		      (TSTEQ I1 (HOLE 1) (INTCONST I2 0)))
		 (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Unordered or Less or Equal ==
;; fbule label
(DEFINST ("fbule ??1D, ?2l" "fbule ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 2))  (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbule,a ??1D, ?2l" "fbule,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 2))  (LABEL I64 (HOLE 2)))
   )
  )

;; == Branch on Ordered ==
;; fbo label
(DEFINST ("fbo ??1D, ?2l" "fbo ??1D, ?2l")
  (PARALLEL
   (DELAYEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 3)) (LABEL I64 (HOLE 2)))
   )
  )

(DEFINST ("fbo,a ??1D, ?2l" "fbo,a ??1D, ?2l")
  (PARALLEL
   (ANNULEDJUMPC (TSTNE I1 (HOLE 1) (INTCONST I2 3)) (LABEL I64 (HOLE 2)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Branch on Integer Condition Codes (Bicc)
;;;
;;; *** Deprecated ***
;;;
;;;	BA	Branch Always
;;;	BN	Branch Never
;;;	BNE	Branch on Not Equal
;;;	BE	Branch on Equal
;;;	BG	Branch on Greater
;;;	BLE	Branch on Less or Equal
;;;	BGE	Branch on Greater or Equal
;;;	BL	Branch on Less
;;;	BGU	Branch on Greater Unsigned
;;;	BLEU	Branch on Less or Equal Unsigned
;;;	BCC	Branch on Carry Clear (Greater than or Equal, Unsigned)
;;;	BCS	Branch on Carry Set (Less than, Unsigned)
;;;	BPOS	Branch on Positive not
;;;	BNEG	Branch on Negative
;;;	BVC	Branch on Overflow Clear
;;;	BVS	Branch on Overflow Set
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Branch Always ==
;; ba label
(DEFINST ("ba ?1l" "ba ?1l")
  (PARALLEL
   (DELAYEDJUMP (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("ba,a ?1l" "ba,a ?1l")
  (PARALLEL
   (JUMP (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch Never ==
;; bn label
;;(DEFINST ("bn ?1l" "bn ?1l")
;;  (PARALLEL
;;   )
;;  )

(DEFINST ("bn,a ?1l" "bn,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (INTCONST I1 0) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Not Equal ==
;; bne label
(DEFINST ("bne ?1l" "bne ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bne,a ?1l" "bne,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Equal ==
;; be label
(DEFINST ("be ?1l" "be ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_z) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("be,a ?1l" "be,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_z) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater ==
;; bg label
(DEFINST ("bg ?1l" "bg ?1l")
  (PARALLEL
   (DELAYEDJUMPC
    (BNOT I1 (BOR I1 (REG I1 icc_z) (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))))
    (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bg,a ?1l" "bg,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC
    (BNOT I1 (BOR I1 (REG I1 icc_z) (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))))
    (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Equal (ANNULED) ==
;; *** be,aと同一のため定義しない ***
;; bz,a label
;;(DEFINST ("bz,a ?1l" "bz,a ?1l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (REG I1 icc_z) (LABEL I64 (HOLE 1)))
;;   )
;;  )

(DEFINST ("ble,a ?1l" "ble,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (REG I1 icc_z)
		      (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater or Equal ==
;; bge label
(DEFINST ("bge ?1l" "bge ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bge,a ?1l" "bge,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
	  (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Less ==
;; bl label
(DEFINST ("bl ?1l" "bl ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bl,a ?1l" "bl,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater Unsigned ==
;; bgu label
(DEFINST ("bgu ?1l" "bgu ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (BOR I1 (REG I1 icc_c) (REG I1 icc_z)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bgu,a ?1l" "bgu,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (BOR I1 (REG I1 icc_c) (REG I1 icc_z)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Less or Equal Unsigned ==
;; bleu label
(DEFINST ("bleu ?1l" "bleu ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (REG I1 icc_c) (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bleu,a ?1l" "bleu,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (REG I1 icc_c) (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Carry Clear ==
;; bcc label
(DEFINST ("bcc ?1l" "bcc ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_c)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcc,a ?1l" "bcc,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_c)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Carry Set ==
;; bcs label
(DEFINST ("bcs ?1l" "bcs ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_c) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcs,a ?1l" "bcs,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_c) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Positive ==
;; bpos label
(DEFINST ("bpos ?1l" "bpos ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_n)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bpos,a ?1l" "bpos,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_n)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Negative ==
;; bneg label
(DEFINST ("bneg ?1l" "bneg ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_n) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bneg,a ?1l" "bneg,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_n) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Overflow Clear ==
;; bvc label
(DEFINST ("bvc ?1l" "bvc ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvc,a ?1l" "bvc,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Overflow Set ==
;; bvs label
(DEFINST ("bvs ?1l" "bvs ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_v) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvs,a ?1l" "bvs,a ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_v) (LABEL I64 (HOLE 1)))
   )
  )

;;;----------------------------------------------------------------------
;;;
;;; Branch on Integer Condition Codes with Prediction (BPcc)
;;;
;;;	BPA	Branch Always
;;;	BPN	Branch Never
;;;	BPNE	Branch on Not Equal
;;;	BPE	Branch on Equal
;;;	BPG	Branch on Greater
;;;	BPLE	Branch on Less or Equal
;;;	BPGE	Branch on Greater or Equal
;;;	BPL	Branch on Less
;;;	BPGU	Branch on Greater Unsigned
;;;	BPLEU	Branch on Less or Equal Unsigned
;;;	BPCC	Branch on Carry Clear (Greater Than or Equal, Unsigned)
;;;	BPCS	Branch on Carry Set (Less than, Unsigned)
;;;	BPPOS	Branch on Positive
;;;	BPNEG	Branch on Negative
;;;	BPVC	Branch on Overflow Clear
;;;	BPVS	Branch on Overflow Set
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Branch Always ==
;; ba label
(DEFINST ("ba %icc, ?1l" "ba %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMP (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("ba %xcc, ?1l" "ba %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMP (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("ba,a %icc, ?1l" "ba,a %icc, ?1l")
  (PARALLEL
   (JUMP (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("ba,a %xcc, ?1l" "ba,a %xcc, ?1l")
  (PARALLEL
   (JUMP (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch Never ==
;; bn label
;;(DEFINST ("bn %icc, ?1l" "bn %icc, ?1l")
;;  (PARALLEL
;;   )
;;  )
;;
;;(DEFINST ("bn %xcc, ?1l" "bn %xcc, ?1l")
;;  (PARALLEL
;;   )
;;  )

(DEFINST ("bn,a %icc, ?1l" "bn,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (INTCONST I1 0) (LABEL I64 (HOLE 1)))
   )
  )

;;(DEFINST ("bn,a %xcc, ?1l" "bn,a %xcc, ?1l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (INTCONST I1 0) (LABEL I64 (HOLE 1)))
;;   )
;;  )

;; == Branch on Not Equal ==
;; bne label
(DEFINST ("bne %icc, ?1l" "bne %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bne %xcc, ?1l" "bne %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 xcc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bne,a %icc, ?1l" "bne,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bne,a %xcc, ?1l" "bne,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 xcc_z)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Equal ==
;; be label
(DEFINST ("be %icc, ?1l" "be %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_z) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("be %xcc, ?1l" "be %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 xcc_z) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("be,a %icc, ?1l" "be,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_z) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("be,a %xcc, ?1l" "be,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 xcc_z) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater ==
;; bg label
(DEFINST ("bg %icc, ?1l" "bg %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC
    (BNOT I1 (BOR I1 (REG I1 icc_z) (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))))
    (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bg %xcc, ?1l" "bg %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC
    (BNOT I1 (BOR I1 (REG I1 xcc_z) (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))))
    (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bg,a %icc, ?1l" "bg,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC
    (BNOT I1 (BOR I1 (REG I1 icc_z) (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))))
    (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bg,a %xcc, ?1l" "bg,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC
    (BNOT I1 (BOR I1 (REG I1 xcc_z) (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))))
    (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Equal (ANNULED) ==
;; *** be,aと同一のため定義しない ***
;; bz,a label
;;(DEFINST ("bz,a %icc, ?1l" "bz,a %icc, ?1l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (REG I1 icc_z) (LABEL I64 (HOLE 1)))
;;   )
;;  )
;;
;;(DEFINST ("bz,a %xcc, ?1l" "bz,a %xcc, ?1l")
;;  (PARALLEL
;;   (ANNULEDJUMPC (REG I1 xcc_z) (LABEL I64 (HOLE 1)))
;;   )
;;  )

(DEFINST ("ble,a %icc, ?1l" "ble,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (REG I1 icc_z)
		      (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("ble,a %xcc, ?1l" "ble,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (REG I1 xcc_z)
		      (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater or Equal ==
;; bge label
(DEFINST ("bge %icc, ?1l" "bge %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bge %xcc, ?1l" "bge %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bge,a %icc, ?1l" "bge,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bge,a %xcc, ?1l" "bge,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Less ==
;; bl label
(DEFINST ("bl %icc, ?1l" "bl %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bl %xcc, ?1l" "bl %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bl,a %icc, ?1l" "bl,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bl,a %xcc, ?1l" "bl,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Greater Unsigned ==
;; bgu label
(DEFINST ("bgu %icc, ?1l" "bgu %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (BOR I1 (REG I1 icc_c) (REG I1 icc_z)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bgu %xcc, ?1l" "bgu %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bgu,a %icc, ?1l" "bgu,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (BOR I1 (REG I1 icc_c) (REG I1 icc_z)))
		 (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bgu,a %xcc, ?1l" "bgu,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z)))
		 (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Less or Equal Unsigned ==
;; bleu label
(DEFINST ("bleu %icc, ?1l" "bleu %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (REG I1 icc_c) (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bleu %xcc, ?1l" "bleu %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bleu,a %icc, ?1l" "bleu,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (REG I1 icc_c) (REG I1 icc_z)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bleu,a %xcc, ?1l" "bleu,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Carry Clear ==
;; bcc label
(DEFINST ("bcc %icc, ?1l" "bcc %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_c)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcc %xcc, ?1l" "bcc %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 xcc_c)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcc,a %icc, ?1l" "bcc,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_c)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcc,a %xcc, ?1l" "bcc,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 xcc_c)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Carry Set ==
;; bcs label
(DEFINST ("bcs %icc, ?1l" "bcs %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_c) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcs %xcc, ?1l" "bcs %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 xcc_c) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcs,a %icc, ?1l" "bcs,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_c) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bcs,a %xcc, ?1l" "bcs,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 xcc_c) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Positive ==
;; bpos label
(DEFINST ("bpos %icc, ?1l" "bpos %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_n)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bpos %xcc, ?1l" "bpos %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 xcc_n)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bpos,a %icc, ?1l" "bpos,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_n)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bpos,a %xcc, ?1l" "bpos,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 xcc_n)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Negative ==
;; bneg label
(DEFINST ("bneg %icc, ?1l" "bneg %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_n) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bneg %xcc, ?1l" "bneg %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 xcc_n) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bneg,a %icc, ?1l" "bneg,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_n) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bneg,a %xcc, ?1l" "bneg,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 xcc_n) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Overflow Clear ==
;; bvc label
(DEFINST ("bvc %icc, ?1l" "bvc %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvc %xcc, ?1l" "bvc %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (BNOT I1 (REG I1 xcc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvc,a %icc, ?1l" "bvc,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 icc_v)) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvc,a %xcc, ?1l" "bvc,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (BNOT I1 (REG I1 xcc_v)) (LABEL I64 (HOLE 1)))
   )
  )

;; == Branch on Overflow Set ==
;; bvs label
(DEFINST ("bvs %icc, ?1l" "bvs %icc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 icc_v) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvs %xcc, ?1l" "bvs %xcc, ?1l")
  (PARALLEL
   (DELAYEDJUMPC (REG I1 xcc_v) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvs,a %icc, ?1l" "bvs,a %icc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 icc_v) (LABEL I64 (HOLE 1)))
   )
  )

(DEFINST ("bvs,a %xcc, ?1l" "bvs,a %xcc, ?1l")
  (PARALLEL
   (ANNULEDJUMPC (REG I1 xcc_v) (LABEL I64 (HOLE 1)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Call and Link
;;;
;;;	CALL	Call and Link
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Call and Link ==
;; call label
(DEFINST ("call ?1l" "call ?1l")
  (PARALLEL
   (SET (REG I64 o7) (REG I64 PC))
   (DELAYEDJUMP (LABEL I64 (HOLE 1)))
   )
  )

;;;----------------------------------------------------------------------
;;;
;;; Compare and Swap
;;;
;;;	CASA	Compare and Swap Word from Alternate space
;;;	CASXA	Compare and Swap Extended from Alternate space
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Compare and Swap ==
;; casa [reg] imm_asi, reg, reg
;; *** Alternate Address Spaceは未サポート ***

;; casa [reg] %asi, reg, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Compare and Swap ==
;; casxa [reg] imm_asi, reg, reg
;; *** Alternate Address Spaceは未サポート ***

;; casxa [reg] %asi, reg, reg
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Divide (64-bit / 32-bit)
;;;
;;; *** Deprecated ***
;;;
;;;	UDIV	Unsigned Integer Divide
;;;	SDIV	Signed Integer Divide
;;;	UDIVcc	Unsigned Integer Divide and modify cc's
;;;	SDIVcc	Signed Integer Divide and modify cc's
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Unsigned Integer Divide ==
;; udiv reg, reg_or_imm, reg
(DEFINST ("udiv ?1r, ??2R, ?3r" "udiv ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTNE I1
			   (BAND I64
			    (DIVU I64 (BOR I64
				       (LSH I64
					(CONVZX I64 (CONVIT I32 (REG I64 Y)))
					(INTCONST I32 32))
				       (CONVZX I64
					(CONVIT I32 (REG I64 (HOLE 1 IREG)))))
				  (CONVZX I64 (CONVIT I32 (HOLE 2))))
			    (INTCONST I64 #xFFFFFFFF00000000))
			   (INTCONST I64 0))
		    (INTCONST I64 #x00000000FFFFFFFF)
		    (CONVZX I64
		     (CONVIT I32
		      (DIVU I64 (BOR I64
				 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
				 (CONVZX I64 (CONVIT I32
						     (REG I64 (HOLE 1 IREG)))))
			    (CONVZX I64 (CONVIT I32 (HOLE 2))))))))
   (CLOBBER (REG I64 Y))
   )
  )

;; destinationがg0の場合はYのみ設定する
;;(DEFINST ("udiv ?1r, ??2R, %g0" "udiv ?1r, ??2R, %g0")
;;  (PARALLEL
;;   (CLOBBER (REG I64 Y))
;;   )
;;  )

;; == Signed Integer Divide ==
;; sdiv reg, reg_or_imm, reg
(DEFINST ("sdiv ?1r, ??2R, ?3r" "sdiv ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTEQ I1
			   (DIVS I64
			    (BOR I64
			     (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				  (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			    (HOLE 2))
			   (CONVSX I64
			    (CONVIT I32
			     (DIVS I64
			      (BOR I64
			       (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			       (CONVZX I64
				       (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			      (HOLE 2)))))
		    (CONVSX I64
		     (CONVIT I32
		      (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
					      (INTCONST I32 32))
				     (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			    (HOLE 2))))
		    (IFTHENELSE I64
				(TSTGES I1
					(DIVS I64
					 (BOR I64
					  (LSH I64 (CONVZX I64 (REG I32 Y))
					       (INTCONST I32 32))
					  (CONVZX I64 (REG I32 (HOLE 1 IREG))))
					 (HOLE 2))
					(INTCONST I64 0))
				(INTCONST I64 #x000000007FFFFFFF)
				(INTCONST I64 #xFFFFFFFF80000000))))
   (CLOBBER (REG I64 Y))
   )
  )

;; destinationがg0の場合はYのみ設定する
;;(DEFINST ("sdiv ?1r, ??2R, ?3r" "sdiv ?1r, ??2R, ?3r")
;;  (PARALLEL
;;   (CLOBBER (REG I64 Y))
;;   )
;;  )

;; == Unsigned Integer Divide and modify icc ==
;; udivcc reg, reg_or_imm, reg
(DEFINST ("udivcc ?1r, ??2R, ?3r" "udivcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTNE I1
			   (BAND I64
			    (DIVU I64
			     (BOR I64
			      (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				   (INTCONST I32 32))
			      (CONVZX I64
				      (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			     (CONVZX I64 (CONVIT I32 (HOLE 2))))
			    (INTCONST I64 #xFFFFFFFF00000000))
			   (INTCONST I64 0))
		    (INTCONST I64 #x00000000FFFFFFFF)
		    (CONVZX I64
		     (CONVIT I32
		      (DIVU I64
		       (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
			    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		       (CONVZX I64 (CONVIT I32 (HOLE 2))))))))
   (CLOBBER (REG I64 Y))
   (SET (REG I1 icc_n)
	(TSTLTS I1
		(CONVIT I32
		 (IFTHENELSE I64
			     (TSTNE I1
				    (BAND I64
				     (DIVU I64
				      (BOR I64
				       (LSH I64
					(CONVZX I64 (CONVIT I32 (REG I64 Y)))
					(INTCONST I32 32))
				       (CONVZX I64
					(CONVIT I32 (REG I64 (HOLE 1 IREG)))))
				      (CONVZX I64 (CONVIT I32 (HOLE 2))))
				     (INTCONST I64 #xFFFFFFFF00000000))
				    (INTCONST I64 0))
			     (INTCONST I64 #x00000000FFFFFFFF)
			     (CONVZX I64
			      (CONVIT I32
			       (DIVU I64
				(BOR I64
				 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
				 (CONVZX I64
					 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
				(CONVZX I64 (CONVIT I32 (HOLE 2))))))))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	       (CONVIT I32
		(IFTHENELSE I64
			    (TSTNE I1
				   (BAND I64
				    (DIVU I64
				     (BOR I64
				      (LSH I64
				       (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				       (INTCONST I32 32))
				      (CONVZX I64
				       (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
				     (CONVZX I64 (CONVIT I32 (HOLE 2))))
				    (INTCONST I64 #xFFFFFFFF00000000))
				   (INTCONST I64 0))
			    (INTCONST I64 #x00000000FFFFFFFF)
			    (CONVZX I64
			     (CONVIT I32
			      (DIVU I64
			       (BOR I64
				(LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
				(CONVZX I64
					(CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			       (CONVZX I64 (CONVIT I32 (HOLE 2))))))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(TSTNE I1
	       (BAND I64
		(DIVU I64
		 (BOR I64
		      (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
			   (INTCONST I32 32))
		      (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		 (CONVZX I64 (CONVIT I32 (HOLE 2))))
		(INTCONST I64 #xFFFFFFFF00000000))
	       (INTCONST I64 0)))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1
	 (IFTHENELSE I64
		     (TSTNE I1
		      (BAND I64
		       (DIVU I64
			(BOR I64
			 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
			      (INTCONST I32 32))
			 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			(CONVZX I64 (CONVIT I32 (HOLE 2))))
		       (INTCONST I64 #xFFFFFFFF00000000))
		      (INTCONST I64 0))
		     (INTCONST I64 #x00000000FFFFFFFF)
		     (CONVZX I64
		      (CONVIT I32
		       (DIVU I64
			(BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			(CONVZX I64 (CONVIT I32 (HOLE 2)))))))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	 (IFTHENELSE I64
		     (TSTNE I1
		      (BAND I64
		       (DIVU I64
			(BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			(CONVZX I64 (CONVIT I32 (HOLE 2))))
		       (INTCONST I64 #xFFFFFFFF00000000))
		      (INTCONST I64 0))
		     (INTCONST I64 #x00000000FFFFFFFF)
		     (CONVZX I64
		      (CONVIT I32
		       (DIVU I64
			(BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			(CONVZX I64 (CONVIT I32 (HOLE 2)))))))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はY、フラグのみ設定する
(DEFINST ("udivcc ?1r, ??2R, %g0" "udivcc ?1r, ??2R, %g0")
  (PARALLEL
   (CLOBBER (REG I64 Y))
   (SET (REG I1 icc_n)
	(TSTLTS I1
	 (CONVIT I32
	  (IFTHENELSE I64
		      (TSTNE I1
		       (BAND I64
			(DIVU I64
			 (BOR I64
			  (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
			       (INTCONST I32 32))
			  (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			 (CONVZX I64 (CONVIT I32 (HOLE 2))))
			(INTCONST I64 #xFFFFFFFF00000000))
		       (INTCONST I64 0))
		      (INTCONST I64 #x00000000FFFFFFFF)
		      (CONVZX I64
		       (CONVIT I32
			(DIVU I64
			 (BOR I64
			  (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
			       (INTCONST I32 32))
			  (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			 (CONVZX I64 (CONVIT I32 (HOLE 2))))))))
	 (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	       (CONVIT I32
		(IFTHENELSE I64
			    (TSTNE I1
			     (BAND I64
			      (DIVU I64
			       (BOR I64
				(LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
				(CONVZX I64
					(CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			       (CONVZX I64 (CONVIT I32 (HOLE 2))))
			      (INTCONST I64 #xFFFFFFFF00000000))
			     (INTCONST I64 0))
			    (INTCONST I64 #x00000000FFFFFFFF)
			    (CONVZX I64
			     (CONVIT I32
			      (DIVU I64
			       (BOR I64
				(LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
				(CONVZX I64
					(CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			       (CONVZX I64 (CONVIT I32 (HOLE 2))))))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(TSTNE I1
	       (BAND I64
		(DIVU I64
		 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
			       (INTCONST I32 32))
		      (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		 (CONVZX I64 (CONVIT I32 (HOLE 2))))
		(INTCONST I64 #xFFFFFFFF00000000))
	       (INTCONST I64 0)))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1
	 (IFTHENELSE I64
		     (TSTNE I1
		      (BAND I64
		       (DIVU I64
			(BOR I64
			 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
			      (INTCONST I32 32))
			 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			(CONVZX I64 (CONVIT I32 (HOLE 2))))
		       (INTCONST I64 #xFFFFFFFF00000000))
		      (INTCONST I64 0))
		     (INTCONST I64 #x00000000FFFFFFFF)
		     (CONVZX I64
		      (CONVIT I32
		       (DIVU I64
		        (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
			(CONVZX I64 (CONVIT I32 (HOLE 2)))))))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	 (IFTHENELSE I64
	  (TSTNE I1
	   (BAND I64
	    (DIVU I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (CONVZX I64 (CONVIT I32 (HOLE 2))))
	    (INTCONST I64 #xFFFFFFFF00000000))
	   (INTCONST I64 0))
	  (INTCONST I64 #x00000000FFFFFFFF)
	  (CONVZX I64
	   (CONVIT I32
	    (DIVU I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (CONVZX I64 (CONVIT I32 (HOLE 2)))))))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; == Signed Integer Divide and modify icc ==
;; sdivcc reg, reg_or_imm, reg
(DEFINST ("sdivcc ?1r, ??2R, ?3r" "sdivcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
         (TSTEQ I1
	  (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				  (INTCONST I32 32))
			 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		(HOLE 2))
	  (CONVSX I64
	   (CONVIT I32
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (HOLE 2)))))
	 (CONVSX I64
	  (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
					      (INTCONST I32 32))
				     (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			    (HOLE 2))))
	 (IFTHENELSE I64
		     (TSTGES I1
			     (DIVS I64
				   (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
						 (INTCONST I32 32))
					(CONVZX I64 (REG I32 (HOLE 1 IREG))))
				   (HOLE 2))
			     (INTCONST I64 0))
		     (INTCONST I64 #x000000007FFFFFFF)
		     (INTCONST I64 #xFFFFFFFF80000000))))
   (CLOBBER (REG I64 Y))
   (SET (REG I1 icc_n)
	(TSTLTS I1
	 (CONVIT I32
	  (IFTHENELSE I64
	   (TSTEQ I1
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (HOLE 2))
	    (CONVSX I64
	     (CONVIT I32
	      (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		    (HOLE 2)))))
	   (CONVSX I64
            (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
						(INTCONST I32 32))
				       (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			      (HOLE 2))))
	   (IFTHENELSE I64
		       (TSTGES I1
			(DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
						(INTCONST I32 32))
				       (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			      (CONVSX I64 (CONVIT I32 (HOLE 2))))
			(INTCONST I64 0))
		       (INTCONST I64 #x000000007FFFFFFF)
		       (INTCONST I64 #xFFFFFFFF80000000))))
	 (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	 (CONVIT I32
	  (IFTHENELSE I64
	   (TSTEQ I1
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (HOLE 2))
	    (CONVSX I64
	     (CONVIT I32
	      (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		    (HOLE 2)))))
	   (CONVSX I64
            (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
						(INTCONST I32 32))
				       (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			      (HOLE 2))))
	   (IFTHENELSE I64
	    (TSTGES I1
	     (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
				     (INTCONST I32 32))
			    (CONVZX I64 (REG I32 (HOLE 1 IREG))))
		   (HOLE 2))
	     (INTCONST I64 0))
	    (INTCONST I64 #x000000007FFFFFFF)
	    (INTCONST I64 #xFFFFFFFF80000000))))
	 (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(TSTNE I1
	  (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				  (INTCONST I32 32))
			 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		(HOLE 2))
	  (CONVSX I64
	   (CONVIT I32
            (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (HOLE 2))))))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1
	 (IFTHENELSE I64
	  (TSTEQ I1
	   (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				   (INTCONST I32 32))
			  (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		 (HOLE 2))
	   (CONVSX I64
            (CONVIT I32
             (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
			    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		   (HOLE 2)))))
	  (CONVSX I64
           (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
					       (INTCONST I32 32))
				      (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			     (HOLE 2))))
	  (IFTHENELSE I64
	   (TSTGES I1
		   (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
					   (INTCONST I32 32))
				  (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			 (HOLE 2))
		   (INTCONST I64 0))
	   (INTCONST I64 #x000000007FFFFFFF)
	   (INTCONST I64 #xFFFFFFFF80000000)))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	 (IFTHENELSE I64
	  (TSTEQ I1
	   (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				   (INTCONST I32 32))
			  (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		 (HOLE 2))
	   (CONVSX I64
	    (CONVIT I32
	     (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
			    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		   (HOLE 2)))))
	  (CONVSX I64
           (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
					       (INTCONST I32 32))
				      (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			     (HOLE 2))))
	  (IFTHENELSE I64
	   (TSTGES I1
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
				    (INTCONST I32 32))
			   (CONVZX I64 (REG I32 (HOLE 1 IREG))))
		  (HOLE 2))
	    (INTCONST I64 0))
	   (INTCONST I64 #x000000007FFFFFFF)
	   (INTCONST I64 #xFFFFFFFF80000000)))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はY、フラグのみ設定する
(DEFINST ("sdivcc ?1r, ??2R, %g0" "sdivcc ?1r, ??2R, %g0")
  (PARALLEL
   (CLOBBER (REG I64 Y))
   (SET (REG I1 icc_n)
	(TSTLTS I1
	 (CONVIT I32
	  (IFTHENELSE I64
	   (TSTEQ I1
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (HOLE 2))
	    (CONVSX I64
             (CONVIT I32
              (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		    (HOLE 2)))))
	   (CONVSX I64
	    (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
						(INTCONST I32 32))
				       (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			      (HOLE 2))))
	   (IFTHENELSE I64
	    (TSTGES I1
	     (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
				     (INTCONST I32 32))
			    (CONVZX I64 (REG I32 (HOLE 1 IREG))))
		   (HOLE 2))
	     (INTCONST I64 0))
	    (INTCONST I64 #x000000007FFFFFFF)
	    (INTCONST I64 #xFFFFFFFF80000000))))
	 (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	 (CONVIT I32
	  (IFTHENELSE I64
	   (TSTEQ I1
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				    (INTCONST I32 32))
			   (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		  (HOLE 2))
	    (CONVSX I64
	     (CONVIT I32
              (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				      (INTCONST I32 32))
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		    (HOLE 2)))))
	   (CONVSX I64
            (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
						(INTCONST I32 32))
				       (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			      (HOLE 2))))
	   (IFTHENELSE I64
	    (TSTGES I1
	     (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
				     (INTCONST I32 32))
			    (CONVZX I64 (REG I32 (HOLE 1 IREG))))
		   (HOLE 2))
	     (INTCONST I64 0))
	    (INTCONST I64 #x000000007FFFFFFF)
	    (INTCONST I64 #xFFFFFFFF80000000))))
	 (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(TSTNE I1
	 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				 (INTCONST I32 32))
			(CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
	       (HOLE 2))
	 (CONVSX I64
          (CONVIT I32
           (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				   (INTCONST I32 32))
			  (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		 (HOLE 2))))))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1
	 (IFTHENELSE I64
	  (TSTEQ I1
	   (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				   (INTCONST I32 32))
			  (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		 (HOLE 2))
	   (CONVSX I64
            (CONVIT I32
             (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
			    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		   (HOLE 2)))))
	  (CONVSX I64
           (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
					       (INTCONST I32 32))
				      (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			     (HOLE 2))))
	  (IFTHENELSE I64
	   (TSTGES I1
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
				    (INTCONST I32 32))
			   (CONVZX I64 (REG I32 (HOLE 1 IREG))))
		  (HOLE 2))
	    (INTCONST I64 0))
	   (INTCONST I64 #x000000007FFFFFFF)
	   (INTCONST I64 #xFFFFFFFF80000000)))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	 (IFTHENELSE I64
	  (TSTEQ I1
	   (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				   (INTCONST I32 32))
			  (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		 (HOLE 2))
	   (CONVSX I64
            (CONVIT I32
             (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (CONVIT I32 (REG I64 Y)))
				     (INTCONST I32 32))
			    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG)))))
		   (HOLE 2)))))
	  (CONVSX I64
           (CONVIT I32 (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
					       (INTCONST I32 32))
				      (CONVZX I64 (REG I32 (HOLE 1 IREG))))
			     (HOLE 2))))
	  (IFTHENELSE I64
           (TSTGES I1
	    (DIVS I64 (BOR I64 (LSH I64 (CONVZX I64 (REG I32 Y))
				    (INTCONST I32 32))
			   (CONVZX I64 (REG I32 (HOLE 1 IREG))))
		  (HOLE 2))
	    (INTCONST I64 0))
	   (INTCONST I64 #x000000007FFFFFFF)
	   (INTCONST I64 #xFFFFFFFF80000000)))
	 (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; DONE and RETRY
;;;
;;;	DONE	Return from Trap (skip trapped instruction)
;;;	RETRY	Return from Trap (retry trapped instruction)
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == DONE and RETRY ==
;; done
;; *** TRAP関連命令は未サポート ***

;; == DONE and RETRY ==
;; retry
;; *** TRAP関連命令は未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Floating-Point Add and Subtract
;;;
;;;	FADDs	Add Single
;;;	FADDd	Add Double
;;;	FADDq	Add Quad
;;;	FSUBs	Subtract Single
;;;	FSUBd	Subtract Double
;;;	FSUBq	Subtract Quad
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Add Single ==
;; fadds freg, freg, freg
(DEFINST ("fadds ??1F, ??2F, ??3F" "fadds ??1F, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3) (ADD F32 (HOLE 1) (HOLE 2)))
   )
)

;; == Add Double ==
;; faddd freg, freg, freg
(DEFINST ("faddd ?1f, ?2f, ?3f" "faddd ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(ADD F64 (REG F64 (HOLE 1 FREG))
	     (REG F64 (HOLE 2 FREG))))
   )
)

;; == Add Quad ==
;; faddq freg, freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Subtract Single ==
;; fsubs freg, freg, freg
(DEFINST ("fsubs ??1F, ??2F, ??3F" "fsubs ??1F, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3) (SUB F32 (HOLE 1) (HOLE 2)))
   )
)

;; == Subtract Double ==
;; fsubd freg, freg, freg
(DEFINST ("fsubd ?1f, ?2f, ?3f" "fsubd ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(SUB F64 (REG F64 (HOLE 1 FREG))
	     (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Subtract Quad ==
;; fsubq freg, freg, freg
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Floating-Point Compare
;;;
;;;	FCMPs	Compare Single
;;;	FCMPd	Compare Double
;;;	FCMPq	Compare Quad
;;;	FCMPEs	Compare Single and Exception if Unordered
;;;	FCMPEd	Compare Double and Exception if Unordered
;;;	FCMPEq	Compare Quad and Exception if Unordered
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Compare Single ==
;; fcmps freg, freg
(DEFINST ("fcmps ??1F, ??2F" "fcmps ??1F, ??2F")
  (PARALLEL
   (SET (REG I2 fcc)
	(IFTHENELSE I2 
		    (BOR I1 
			 (NOTANUMBER I1 (HOLE 1))
			 (NOTANUMBER I1 (HOLE 2)))
		    (INTCONST I2 3)
		    (IFTHENELSE I2 (TSTEQ I1 (HOLE 1) (HOLE 2))
				(INTCONST I2 0)
				(IFTHENELSE I2 (TSTLTS I1 (HOLE 1) (HOLE 2))
					    (INTCONST I2 1)
					    (INTCONST I2 2)))))
   )
  )

;; == Compare Double ==
;; fcmpd freg, freg
(DEFINST ("fcmpd ?1f, ?2f" "fcmpd ?1f, ?2f")
  (PARALLEL
   (SET (REG I2 fcc)
	(IFTHENELSE I2 
		    (BOR I1 
			 (NOTANUMBER I1 (REG F64 (HOLE 1 FREG)))
			 (NOTANUMBER I1 (REG F64 (HOLE 2 FREG))))
		    (INTCONST I2 3)
		    (IFTHENELSE I2 (TSTEQ I1 (REG F64 (HOLE 1 FREG))
					  (REG F64 (HOLE 2 FREG)))
				(INTCONST I2 0)
				(IFTHENELSE I2
					    (TSTLTS I1 (REG F64 (HOLE 1 FREG))
						    (REG F64 (HOLE 2 FREG)))
					    (INTCONST I2 1)
					    (INTCONST I2 2)))))
   )
  )

;; == Compare Quad ==
;; fcmpq freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Compare Single and Exception if Unordered ==
;; fcmpes freg, freg
;; *** 例外は未サポート ***

;; == Compare Double and Exception if Unordered ==
;; fcmped freg, freg
;; *** 例外は未サポート ***

;; == Compare Quad and Exception if Unordered ==
;; fcmpeq freg, freg
;; *** Quad Floating-Pointは未サポート ***
;; *** 例外は未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Convert Floating-Point to Integer
;;;
;;;	FsTOx	Convert Single to 64-bit Integer
;;;	FdTOx	Convert Double to 64-bit Integer
;;;	FqTOx	Convert Quad to 64-bit Integer
;;;	FsTOi	Convert Single to 32-bit Integer
;;;	FdTOi	Convert Double to 32-bit Integer
;;;	FqTOi	Convert Quad to 32-bit Integer
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Convert Single to 64-bit Integer ==
;; fstox freg, freg
(DEFINST ("fstox ??1F, ?2f" "fstox ??1F, ?2f")
  (PARALLEL
   (SET (REG I64 (HOLE 2 FREG)) (CONVFID I64 (HOLE 1)))
   )
  )

;; == Convert Double to 64-bit Integer ==
;; fdtox freg, freg
(DEFINST ("fdtox ?1f, ?2f" "fdtox ?1f, ?2f")
  (PARALLEL
   (SET (REG I64 (HOLE 2 FREG)) (CONVFID I64 (REG F64 (HOLE 1 FREG))))
   )
  )

;; == Convert Quad to 64-bit Integer ==
;; fqtox freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Convert Single to Integer ==
;; fstoi freg, freg
(DEFINST ("fstoi ??1F, ?2g" "fstoi ??1F, ?2g")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 2 FREG)) 0)
	(CONVFID I32 (HOLE 1)))
   )
  )

(DEFINST ("fstoi ??1F, ?2G" "fstoi ??1F, ?2G")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 2 FREG)) 1)
	(CONVFID I32 (HOLE 1)))
   )
  )

;; == Convert Double to Integer ==
;; fdtoi freg, freg
(DEFINST ("fdtoi ?1f, ?2g" "fdtoi ?1f, ?2g")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 2 FREG)) 0)
	(CONVFID I32 (CONVFT F32 (REG F64 (HOLE 1 FREG)))))
   )
  )

(DEFINST ("fdtoi ?1f, ?2G" "fdtoi ?1f, ?2G")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 2 FREG)) 1)
	(CONVFID I32 (CONVFT F32 (REG F64 (HOLE 1 FREG)))))
   )
  )

;; == Convert Quad to Integer ==
;; fqtoi freg, freg
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Convert Between Floating-Point Formats
;;;
;;;	FsTOd	Convert Single to Double
;;;	FsTOq	Convert Single to Quad
;;;	FdTOs	Convert Double to Single
;;;	FdTOq	Convert Double to Quad
;;;	FqTOs	Convert Quad to Single
;;;	FqTOd	Convert Quad to Double
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Convert Single to Double ==
;; fstod freg, freg
(DEFINST ("fstod ??1F, ?2f" "fstod ??1F, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG)) (CONVFX F64 (HOLE 1)))
   )
  )

;; == Convert Single to Quad ==
;; fstoq freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Convert Double to Single ==
;; fdtos freg, freg
(DEFINST ("fdtos ?1f, ??2F" "fdtos ?1f, ??2F")
  (PARALLEL
   (SET (HOLE 2) (CONVFT F32 (REG F64 (HOLE 1 FREG))))
   )
  )

;; == Convert Double to Quad ==
;; fdtoq freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Convert Quad to Single ==
;; fqtos freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Convert Quad to Double ==
;; fqtod freg, freg
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Convert Integer to Floating-Point
;;;
;;;	FxTOs	Convert 64-bit Integer to Single
;;;	FxTOd	Convert 64-bit Integer to Double
;;;	FxTOq	Convert 64-bit Integer to Quad
;;;	FiTOs	Convert 32-bit Integer to Single
;;;	FiTOd	Convert 32-bit Integer to Double
;;;	FiTOq	Convert 32-bit Integer to Quad
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Convert 64-bit Integer to Single ==
;; fxtos freg, freg
(DEFINST ("fxtos ?1f, ??2F" "fxtos ?1f, ??2F")
  (PARALLEL
   (SET (HOLE 2) (CONVSF F32 (REG I64 (HOLE 1 FREG))))
   )
  )

;; == Convert 64-bit Integer to Double ==
;; fxtod freg, freg
(DEFINST ("fxtod ?1f, ?2f" "fxtod ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG)) (CONVSF F64 (REG I64 (HOLE 1 FREG))))
   )
  )

;; == Convert 64-bit Integer to Quad ==
;; fxtoq freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Convert 32-bit Integer to Single ==
;; fitos freg, freg
(DEFINST ("fitos ?1g, ??2F" "fitos ?1g, ??2F")
  (PARALLEL
   (SET (HOLE 2) (CONVSF F32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 0)))
   )
  )

(DEFINST ("fitos ?1G, ??2F" "fitos ?1G, ??2F")
  (PARALLEL
   (SET (HOLE 2) (CONVSF F32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 1)))
   )
  )

;; == Convert 32-bit Integer to Double ==
;; fitod freg, freg
(DEFINST ("fitod ?1g, ?2f" "fitod ?1g, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(CONVSF F64 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 0)))
   )
  )

(DEFINST ("fitod ?1G, ?2f" "fitod ?1G, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(CONVSF F64 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 1)))
   )
  )

;; == Convert 32-bit Integer to Quad ==
;; fitoq freg, freg
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Floating-Point Move
;;;
;;;	FMOVs	Move Single
;;;	FMOVd	Move Double
;;;	FMOVq	Move Quad
;;;	FNEGs	Negate Single
;;;	FNEGd	Negate Double
;;;	FNEGq	Negate Quad
;;;	FABSs	Absolute Value Single
;;;	FABSd	Absolute Value Double
;;;	FABSq	Absolute Value Quad
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Move Single ==
;; fmovs freg, freg
(DEFINST ("fmovs ??1F, ??2F" "fmovs ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2) (HOLE 1))
   )
  )

;; == Move Double ==
;; fmovd freg, freg
(DEFINST ("fmovd ?1f, ?2f" "fmovd ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG)) (REG F64 (HOLE 1 FREG)))
   )
  )

;; == Move Quad ==
;; fmovq freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Negate Single ==
;; fnegs freg, freg
(DEFINST ("fnegs ??1F, ??2F" "fnegs ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2) (NEG F32 (HOLE 1)))
   )
  )

;; == Negate Double ==
;; fnegd freg, freg
(DEFINST ("fnegd ?1f, ?2f" "fnegd ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG)) (NEG F64 (REG F64 (HOLE 1 FREG))))
   )
  )

;; == Negate Quad ==
;; fnegq freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Absolute Value Single ==
;; fabss freg, freg
(DEFINST ("fabss ??1F, ??2F" "fabss ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (TSTLTS I1 (HOLE 1) (FLOATCONST F32 0.0))
		    (NEG F32 (HOLE 1))
		    (HOLE 1)))
   )
  )

;; == Absolute Value Double ==
;; fabsd freg, freg
(DEFINST ("fabsd ?1f, ?2f" "fabs ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64
		    (TSTLTS I1 (REG F64 (HOLE 1 FREG)) (FLOATCONST F64 0.0))
		    (NEG F64 (REG F64 (HOLE 1 FREG)))
		    (REG F64 (HOLE 1 FREG))))
   )
  )

;; == Absolute Value Quad ==
;; fabsq freg, freg
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Floating-Point Multiply and Divide
;;;
;;;	FMULs	Multiply Single
;;;	FMULd	Multiply Double
;;;	FMULq	Multiply Quad
;;;	FsMULd	Multiply Single to Double
;;;	FdMULq	Multiply Double to Quad
;;;	FDIVs	Divide Single
;;;	FDIVd	Divide Double
;;;	FDIVq	Divide Quad
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Multiply Single ==
;; fmuls freg, freg, freg
(DEFINST ("fmuls ??1F, ??2F, ??3F" "fmuls ??1F, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3) (MUL F32 (HOLE 1) (HOLE 2)))
   )
  )

;; == Multiply Double ==
;; fmuld freg, freg
(DEFINST ("fmuld ?1f, ?2f, ?3f" "fmuld ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(MUL F64 (REG F64 (HOLE 1 FREG)) (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Multiply Quad ==
;; fmulq freg, freg, freg
;; *** Quad Floating-Pointは未サポート ***


;; == Multiply Single to Double ==
;; fsmuld freg, freg, freg
(DEFINST ("fsmuld ??1F, ??2F, ?3f" "fsmuld ??1F, ??2F, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(MUL F64 (CONVFX F64 (HOLE 1)) (CONVFX F64 (HOLE 2))))
   )
  )

;; == Multiply Double to Quad ==
;; fdulq freg, freg, freg
;; *** Quad Floating-Pointは未サポート ***

;; == Divide Single ==
;; fdivs freg, freg
(DEFINST ("fdivs ??1F, ??2F, ??3F" "fdivs ??1F, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3) (DIVS F32 (HOLE 1) (HOLE 2)))
   )
  )

;; == Divide Double ==
;; fdivd freg, freg
(DEFINST ("fdivd ?1f, ?2f, ?3f" "fdivd ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(DIVS F64 (REG F64 (HOLE 1 FREG))
	      (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Divide Quad ==
;; fdivq freg, freg, freg
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Floating-Point Square Root
;;;
;;;	FSQRTs	Square Root Single
;;;	FSQRTd	Square Root Double
;;;	FSQRTq	Square Root Quad
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Square Root Single ==
;; fsqrts freg, freg
;; /// 中間言語で表現不可 /// 

;; == Square Root Double ==
;; fsqrtd freg, freg
;; /// 中間言語で表現不可 /// 

;; == Square Root Quad ==
;; fsqrtq freg, freg
;; /// 中間言語で表現不可 /// 
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Flush Instruction Memory
;;;
;;;	FLUSH	Flush Instruction Memory
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Flush Instruction Memory ==
;; flush address
;; *** Flush Instruction Memoryは未サポート ***
;;(DEFINST "flush address")


;;;----------------------------------------------------------------------
;;;
;;; Flush Register Windows
;;;
;;;	FLUSHW	Flush Register Windows
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Flush Register Windows ==
;; flushw address
;; *** Flush Register Windowsは未サポート ***
;;(DEFINST "flushw address")


;;;----------------------------------------------------------------------
;;;
;;; Illegal Instruction Trap
;;;
;;;	ILLTRAP	Illegal Instruction Trap
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Illegal Instruction Trap ==
;; illtrap const22
;; *** TRAP関連命令は未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Implementation-Dependent Instructions
;;;
;;;	IMPDEP1	Implementation-Dependent Instruction 1
;;;	IMPDEP2	Implementation-Dependent Instruction 2
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Implementation-Dependent Instructions ==
;; *** 未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Jump and Link
;;;
;;;	JMPL	Jump and Link
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Jump and Link ==
;; jmpl label, reg
(DEFINST ("jmpl ??1L, ?2r" "jmpl ??1L, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D)) (REG I64 PC))
   (DELAYEDJUMP (HOLE 1))
   )
  )

;; destinationがg0の場合はリンク情報を保存しない
(DEFINST ("jmpl ??1L, %g0" "jmpl ??1L, %g0")
  (PARALLEL
   (DELAYEDJUMP (HOLE 1))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Load Floating-Point
;;;
;;;	LDF	Load Floating-Point Register
;;;	LDDF	Load Double Floating-Point Register
;;;	LDQF	Load Quad Floating-Point Register
;;;	LDFSR	Load Floating-Point State Register Lower
;;;	LDXFSR	Load Floating-Point State Register
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Load Floating-point Register ==
;; ld [address], freg
(DEFINST ("ld [??1A], ??2F" "ld [??1A], ??2F")
  (PARALLEL
   (SET (HOLE 2) (MEM F32 (HOLE 1)))
   )
  )

;; == Load Double Floatgin-point Register ==
;; ldd [address], freg
(DEFINST ("ld [??1A], ?2f" "ld [??1A], ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG)) (MEM F64 (HOLE 1)))
   )
  )

;; == Load Quad Floating-Point Register ==
;; ldq [address], freg
;; *** Quad Floating-Pointは未サポート ***

;; == Load Floating-point State Register Lower ==
;; ld [address], %fsr
;; *** fsrは未サポート(fccのみサポート) ***

;; == Load Floating-point State Register Lower ==
;; ldx [address], %fsr
;; *** fsrは未サポート(fccのみサポート) ***


;;;----------------------------------------------------------------------
;;;
;;; Load Floating-Point from Alternate Space
;;;
;;;	LDFA	Load Floating-Point Register from Alternate space
;;;	LDDFA	Load Double Floating-Point Register from Alternate space
;;;	LDQFA	Load QuadFloating-Point Register from Alternate space
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Load Floating-Point Register from Alternate space ==
;; lda [regaddr] imm_asi, freg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Floating-Point Register from Alternate space ==
;; lda [reg_plus_imm] %asi, freg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Double Floating-Point Register from Alternate space ==
;; ldda [regaddr] imm_asi, freg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Double Floating-Point Register from Alternate space ==
;; ldda [reg_plus_imm] %asi, freg
;; *** Alternate Address Spaceは未サポート ***

;; == Load QuadFloating-Point Register from Alternate space ==
;; ldqa [regaddr] imm_asi, freg
;; *** Alternate Address Spaceは未サポート ***
;; *** Quad Floating-Pointは未サポート ***

;; == Load QuadFloating-Point Register from Alternate space ==
;; ldqa [reg_plus_imm] %asi, freg
;; *** Alternate Address Spaceは未サポート ***
;; *** Quad Floating-Pointは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Load Integer
;;;
;;;	LDSB	Load Signed Byte
;;;	LDSH	Load Signed Halfword
;;;	LDSW	Load Signed Word
;;;	LDUB	Load Unsigned Byte
;;;	LDUH	Load Unsigned Halfword
;;;	LDUW	Load Unsigned Word
;;;	LDX	Load Extended Word
;;;	LDD	Load Doubleword *** Deprecated ***
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Load Signed Byte ==
;; ldsb [address], reg
(DEFINST ("ldsb [??1A], ?2r" "ldsb [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(CONVSX I64 (MEM I8 (HOLE 1))))
   )
  )

;; == Load Signed Halfword ==
;; ldsh [address], reg
(DEFINST ("ldsh [??1A], ?2r" "ldsh [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(CONVSX I64 (MEM I16 (HOLE 1))))
   )
  )

;; == Load Signed Word ==
;; ldsw [address], reg
(DEFINST ("ldsw [??1A], ?2r" "ldsw [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(CONVSX I64 (MEM I32 (HOLE 1))))
   )
  )

;; == Load Unsigned Byte ==
;; ldub [address], reg
(DEFINST ("ldub [??1A], ?2r" "ldub [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(CONVZX I64 (MEM I8 (HOLE 1))))
   )
  )

;; == Load Unsigned Halfword ==
;; lduh [address], reg
(DEFINST ("lduh [??1A], ?2r" "lduh [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(CONVZX I64 (MEM I16 (HOLE 1))))
   )
  )

;; == Load Unsigned Word ==
;; lduw [address], reg (synonym: ld)
(DEFINST ("lduw [??1A], ?2r" "lduw [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(CONVZX I64 (MEM I32 (HOLE 1))))
   )
  )

;; == Load Extended Word ==
;; ldx [address], reg
(DEFINST ("ldx [??1A], ?2r" "ldx [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D)) (MEM I64 (HOLE 1)))
   )
  )

;; == Load Doubleword ==
;; ldd [address], reg
(DEFINST ("ldd [??1A], %g0" "ldd [??1A], %g0")
  (PARALLEL
   (SET (REG I64 g1)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %g2" "ldd [??1A], %g2")
  (PARALLEL
   (SET (REG I64 g2)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 g3)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %g4" "ldd [??1A], %g4")
  (PARALLEL
   (SET (REG I64 g4)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 g5)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %g6" "ldd [??1A], %g6")
  (PARALLEL
   (SET (REG I64 g6)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 g7)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %o0" "ldd [??1A], %o0")
  (PARALLEL
   (SET (REG I64 o0)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 o1)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %o2" "ldd [??1A], %o2")
  (PARALLEL
   (SET (REG I64 o2)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 o3)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %o4" "ldd [??1A], %o4")
  (PARALLEL
   (SET (REG I64 o4)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 o5)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %o6" "ldd [??1A], %o6")
  (PARALLEL
   (SET (REG I64 o6)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 o7)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %l0" "ldd [??1A], %l0")
  (PARALLEL
   (SET (REG I64 l0)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 l1)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %l2" "ldd [??1A], %l2")
  (PARALLEL
   (SET (REG I64 l2)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 l3)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %l4" "ldd [??1A], %l4")
  (PARALLEL
   (SET (REG I64 l4)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 l5)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %l6" "ldd [??1A], %l6")
  (PARALLEL
   (SET (REG I64 l6)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 l7)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %i0" "ldd [??1A], %i0")
  (PARALLEL
   (SET (REG I64 i0)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 i1)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %i2" "ldd [??1A], %i2")
  (PARALLEL
   (SET (REG I64 i2)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 i3)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %i4" "ldd [??1A], %i4")
  (PARALLEL
   (SET (REG I64 i4)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 i5)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )

(DEFINST ("ldd [??1A], %i6" "ldd [??1A], %i6")
  (PARALLEL
   (SET (REG I64 i6)
	(CONVZX I64 (CONVIT I32 (MEM I64 (HOLE 1)))))
   (SET (REG I64 i7)
	(RSHU I64 (MEM I64 (HOLE 1)) (INTCONST I32 32)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Load Integer from Alternate Space
;;;
;;;	LDSBA	Load Signed Byte from Alternate space
;;;	LDSHA	Load Signed Halfword from Alternate space
;;;	LDSWA	Load Signed Word from Alternate space
;;;	LDUBA	Load Unsigned Byte from Alternate space
;;;	LDUHA	Load Unsigned Halfword from Alternate space
;;;	LDUWA	Load Unsigned Word from Alternate space
;;;	LDXA	Load Extended Word from Alternate space
;;;	LDDA	Load Doubleword from Alternate space
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Load Signed Byte from Alternate space ==
;; ldsba [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Signed Halfword from Alternate space ==
;; ldsha [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Signed Word from Alternate space ==
;; ldswa [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Unsigned Byte from Alternate space ==
;; lduba [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Unsigned Halfword from Alternate space ==
;; lduha [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Unsigned Word from Alternate space ==
;; lduwa [regaddr] imm_asi, reg (synonym: lda)
;; *** Alternate Address Spaceは未サポート ***

;; == Load Extended Word from Alternate space ==
;; ldxa [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Doubleword from Alternate space ==
;; ldda [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Signed Byte from Alternate space ==
;; ldsba [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Signed Halfword from Alternate space ==
;; ldsha [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Signed Word from Alternate space ==
;; ldswa [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Unsigned Byte from Alternate space ==
;; lduba [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Unsigned Halfword from Alternate space ==
;; lduha [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Unsigned Word from Alternate space ==
;; lduwa [reg_plus_imm] %asi, reg (synonym: lda)
;; *** Alternate Address Spaceは未サポート ***

;; == Load Extended Word from Alternate space ==
;; ldxa [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Load Doubleword from Alternate space ==
;; ldda [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Load-Store Unsigned Byte
;;;
;;;	LDSTUB	Load-Store Unsigned Byte
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Atomic Load-Store Unsigned Byte ==
;; ldstub [address], reg
(DEFINST ("ldstub [??1A], ?2r" "ldstub [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D)) (CONVZX I64 (MEM I8 (HOLE 1))))
   (SET (MEM I8 (HOLE 1)) (INTCONST I8 #xff))
   )
  )

;; destinationがg0の場合はメモリのみ設定
(DEFINST ("ldstub [??1A], %g0" "ldstub [??1A], %g0")
  (PARALLEL
   (SET (MEM I8 (HOLE 1)) (INTCONST I8 #xff))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Load-Store Unsigned Byte to Alternate Space
;;;
;;;	LDSTUBA	Load-Store Unsigned Byte into Alternate space
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Atomic Load-Store Unsigned Byte into Alternate space ==
;; ldstuba [regaddr] imm_asi, reg
;; *** Alternate Address Spaceは未サポート ***

;; == Atomic Load-Store Unsigned Byte into Alternate space ==
;; ldstuba [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Logical Operations
;;;
;;;	AND	And
;;;	ANDcc	And and modify cc's
;;;	ANDN	And Not
;;;	ANDNcc	And Not and modify cc's
;;;	OR	Inclusive Or
;;;	ORcc	Inclusive Or and modify cc's
;;;	ORN	Inclusive Or Not
;;;	ORNcc	Inclusive Or Not and modify cc's
;;;	XOR	Exclusive Or
;;;	XORcc	Exclusive Or and modify cc's
;;;	XNOR	Exclusive Nor
;;;	XNORcc	Exclusive Nor and modify cc's
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == And ==
;; and reg, reg_or_imm, reg
(DEFINST ("and ?1r, ??2R, ?3r" "and ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == And and modify icc ==
;; andcc reg, reg_or_imm, reg
(DEFINST ("andcc ?1r, ??2R, ?3r" "andcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はフラグ設定のみ
(DEFINST ("andcc ?1r, ??2R, %g0" "andcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; == And Not ==
;; andn reg, reg_or_imm, reg
(DEFINST ("andn ?1r, ??2R, ?3r" "andn ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
   )
  )

;; == And Not and modify icc ==
;; andncc reg, reg_or_imm, reg
(DEFINST ("andncc ?1r, ??2R, ?3r" "andncc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
   (SET (REG I1 icc_n)
	(TSTLTS I1
		(CONVIT I32
			(BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	       (CONVIT I32
		       (BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はフラグ設定のみ
(DEFINST ("andncc ?1r, ??2R, %g0" "andncc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1
		(CONVIT I32
			(BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32
		   (BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BAND I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; == Inclusive Or ==
;; or reg, reg_or_imm, reg
(DEFINST ("or ?1r, ??2R, ?3r" "or ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Inclusive Or and modify icc ==
;; orcc reg, reg_or_imm, reg
(DEFINST ("orcc ?1r, ??2R, ?3r" "orcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はフラグ設定のみ
(DEFINST ("orcc ?1r, ??2R, %g0" "orcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; ==  Inclusive Or Not ==
;; orn reg, reg_or_imm, reg
(DEFINST ("orn ?1r, ??2R, ?3r" "orn ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
   )
  )

;;
;; == Inclusive Or Not and modify icc ==
;; orncc reg, reg_or_imm, reg
(DEFINST ("orncc ?1r, ??2R, ?3r" "orncc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG))
				    (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG))
				   (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はフラグ設定のみ
(DEFINST ("orncc ?1r, ??2R, %g0" "orncc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG))
				    (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BOR I64 (REG I64 (HOLE 1 IREG))
				   (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; == Exclusive Or ==
;; xor reg, reg_or_imm, reg
(DEFINST ("xor ?1r, ??2R, ?3r" "xor ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Exclusive Or and modify icc ==
;; xorcc reg, reg_or_imm, reg
(DEFINST ("xorcc ?1r, ??2R, ?3r" "xorcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はフラグ設定のみ
(DEFINST ("xorcc ?1r, ??2R, %g0" "xorcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; == Exclusive Nor ==
;; xnor reg, reg_or_imm, reg
(DEFINST ("xnor ?1r, ??2R, ?3r" "xnor ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BXOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
   )
  )

;; == Exclusive Nor and modify icc ==
;; xnorcc reg, reg_or_imm, reg
(DEFINST ("xnorcc ?1r, ??2R, ?3r" "xnorcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BXOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG))
				     (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG))
				    (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はフラグ設定のみ
(DEFINST ("xnorcc ?1r, ??2R, %g0" "xnorcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG))
				     (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (BXOR I64 (REG I64 (HOLE 1 IREG))
				    (BNOT I64 (HOLE 2))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (BXOR I64 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Memory Barrier
;;;
;;;	MEMBAR	Memory Barrier
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Memory Barrier ==
;; membar membar_mask
;; *** Memory Barrierは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Move Floating-Point Register on Condition (FMOVcc)
;;;
;;;	FMOVA	Move Always
;;;	FMOVN	Move Never
;;;	FMOVNE	Move if Not Equal
;;;	FMOVE	Move if Equal
;;;	FMOVG	Move if Greater
;;;	FMOVLE	Move if Less or Equal
;;;	FMOVGE	Move if Greater or Equal
;;;	FMOVL	Move if Less
;;;	FMOVGU	Move if Greater Unsigned
;;;	FMOVLEU	Move if Less or Equal Unsigned
;;;	FMOVCC	Move if Carry Clear (Greater or Equal, Unsigned)
;;;	FMOVCS	Move if Carry Set (Less than, Unsigned)
;;;	FMOVPOS	Move if Positive
;;;	FMOVNEG	Move if Negative
;;;	FMOVVC	Move if Overflow Clear
;;;	FMOVVS	Move if Overflow Set
;;;
;;;	FMOVFA	Move Always
;;;	FMOVFN	Move Never
;;;	FMOVFU	Move if Unordered
;;;	FMOVFG	Move if Greater
;;;	FMOVFUG	Move if Unordered or Greater
;;;	FMOVFL	Move if Less
;;;	FMOVFUL	Move if Unordered or Less
;;;	FMOVFLG	Move if Less or Greater
;;;	FMOVFNE	Move if Not Equal
;;;	FMOVFE	Move if Equal
;;;	FMOVFUE	Move if Unordered or Equal
;;;	FMOVFGE	Move if Greater or Equal
;;;	FMOVFUGE Move if Unordered or Greater or Equal
;;;	FMOVFLE	Move if Less or Equal
;;;	FMOVFULE Move if Unordered or Less or Equal
;;;	FMOVFO	Move if Ordered
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Move Always ==
;; fmov{s,d,q}a i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsa %icc, ??1F, ??2F" "fmovsa %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (INTCONST I1 1)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsa %xcc, ??1F, ??2F" "fmovsa %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (INTCONST I1 1)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovda %icc, ?1f, ?2f" "fmovda %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (INTCONST I1 1)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovda %xcc, ?1f, ?2f" "fmovda %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (INTCONST I1 1)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move Never ==
;; fmov{s,d,q}n i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsn %icc, ??1F, ??2F" "fmovsn %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (INTCONST I1 0)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsn %xcc, ??1F, ??2F" "fmovsn %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (INTCONST I1 0)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdn %icc, ?1f, ?2f" "fmovdn %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (INTCONST I1 0)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdn %xcc, ?1f, ?2f" "fmovdn %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (INTCONST I1 0)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Not Equal ==
;; fmov{s,d,q}ne i_or_x_cc, freg, freg (synonyms: fmov{s,d,q}nz)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsne %icc, ??1F, ??2F" "fmovsne %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 icc_z))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsne %xcc, ??1F, ??2F" "fmovsne %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 xcc_z))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdne %icc, ?1f, ?2f" "fmovdne %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 icc_z))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdne %xcc, ?1f, ?2f" "fmovdne %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 xcc_z))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Equal ==
;; fmov{s,d,q}e i_or_x_cc, freg, freg (synonyms: fmov{s,d,q}z)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovse %icc, ??1F, ??2F" "fmovse %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 icc_z)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovse %xcc, ??1F, ??2F" "fmovse %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 xcc_z)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovde %icc, ?1f, ?2f" "fmovde %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 icc_z)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovde %xcc, ?1f, ?2f" "fmovde %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 xcc_z)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Greater ==
;; fmov{s,d,q}g i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsg %icc, ??1F, ??2F" "fmovsg %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (BOR I1 (REG I1 icc_z)
				      (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsg %xcc, ??1F, ??2F" "fmovsg %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (BOR I1 (REG I1 xcc_z)
				      (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdg %icc, ?1f, ?2f" "fmovdg %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (BOR I1 (REG I1 icc_z)
				      (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdg %xcc, ?1f, ?2f" "fmovdg %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (BOR I1 (REG I1 xcc_z)
				      (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Less or Equal ==
;; fmov{s,d,q}le i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsle %icc, ??1F, ??2F" "fmovsle %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BOR I1 (REG I1 icc_z)
			     (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsle %xcc, ??1F, ??2F" "fmovsle %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BOR I1 (REG I1 xcc_z)
			     (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdle %icc, ?1f, ?2f" "fmovdle %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BOR I1 (REG I1 icc_z)
			     (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdle %xcc, ?1f, ?2f" "fmovdle %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BOR I1 (REG I1 xcc_z)
			     (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Greater or Equal ==
;; fmov{s,d,q}ge i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsge %icc, ??1F, ??2F" "fmovsge %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsge %xcc, ??1F, ??2F" "fmovsge %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdge %icc, ?1f, ?2f" "fmovdge %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdge %xcc, ?1f, ?2f" "fmovdge %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Less ==
;; fmov{s,d,q}l i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsl %icc, ??1F, ??2F" "fmovsl %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsl %xcc, ??1F, ??2F" "fmovsl %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdl %icc, ?1f, ?2f" "fmovdl %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdl %xcc, ?1f, ?2f" "fmovdl %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Greater Unsigned ==
;; fmov{s,d,q}gu i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsgu %icc, ??1F, ??2F" "fmovsgu %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (BOR I1 (REG I1 icc_c) (REG I1 icc_z)))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsgu %xcc, ??1F, ??2F" "fmovsgu %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z)))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdgu %icc, ?1f, ?2f" "fmovdgu %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (BOR I1 (REG I1 icc_c) (REG I1 icc_z)))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdgu %xcc, ?1f, ?2f" "fmovdgu %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z)))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Less or Equal Unsigned ==
;; fmov{s,d,q}leu i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsleu %icc, ??1F, ??2F" "fmovsleu %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BOR I1 (REG I1 icc_c) (REG I1 icc_z))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsleu %xcc, ??1F, ??2F" "fmovsleu %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdleu %icc, ?1f, ?2f" "fmovdleu %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BOR I1 (REG I1 icc_c) (REG I1 icc_z))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdleu %xcc, ?1f, ?2f" "fmovdleu %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Carry Clear (Greater or Equal, Unsigned) ==
;; fmov{s,d,q}cc i_or_x_cc, freg, freg (synonyms: fmov{s,d,q}geu)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovscc %icc, ??1F, ??2F" "fmovscc %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 icc_c))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovscc %xcc, ??1F, ??2F" "fmovscc %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 xcc_c))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdcc %icc, ?1f, ?2f" "fmovdcc %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 icc_c))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdcc %xcc, ?1f, ?2f" "fmovdcc %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 xcc_c))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Carry Set (Less than, Unsigned) ==
;; fmov{s,d,q}cs i_or_x_cc, freg, freg (synonyms: fmov{s,d,q}lu)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovscs %icc, ??1F, ??2F" "fmovscs %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 icc_c)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovscs %xcc, ??1F, ??2F" "fmovscs %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 xcc_c)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdcs %icc, ?1f, ?2f" "fmovdcs %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 icc_c)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdcs %xcc, ?1f, ?2f" "fmovdcs %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 xcc_c)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Positive ==
;; fmov{s,d,q}pos i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovspos %icc, ??1F, ??2F" "fmovspos %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 icc_n))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovspos %xcc, ??1F, ??2F" "fmovspos %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 xcc_n))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdpos %icc, ?1f, ?2f" "fmovdpos %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 icc_n))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdpos %xcc, ?1f, ?2f" "fmovdpos %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 xcc_n))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Negative ==
;; fmov{s,d,q}neg i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsneg %icc, ??1F, ??2F" "fmovsneg %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 icc_n)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsneg %xcc, ??1F, ??2F" "fmovsneg %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 xcc_n)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdneg %icc, ?1f, ?2f" "fmovdneg %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 icc_n)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdneg %xcc, ?1f, ?2f" "fmovdneg %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 xcc_n)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Overflow Clear ==
;; fmov{s,d,q}vc i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsvc %icc, ??1F, ??2F" "fmovsvc %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 icc_v))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsvc %xcc, ??1F, ??2F" "fmovsvc %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (BNOT I1 (REG I1 xcc_v))
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdvc %icc, ?1f, ?2f" "fmovdvc %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 icc_v))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdvc %xcc, ?1f, ?2f" "fmovdvc %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (BNOT I1 (REG I1 xcc_v))
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move if Overflow Set ==
;; fmov{s,d,q}vs i_or_x_cc, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsvs %icc, ??1F, ??2F" "fmovsvs %icc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 icc_v)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovsvs %xcc, ??1F, ??2F" "fmovsvs %xcc, ??1F, ??2F")
  (PARALLEL
   (SET (HOLE 2)
	(IFTHENELSE F32 (REG I1 xcc_v)
		    (HOLE 1)
		    (HOLE 2)))
   )
  )

(DEFINST ("fmovdvs %icc, ?1f, ?2f" "fmovdvs %icc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 icc_v)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

(DEFINST ("fmovdvs %xcc, ?1f, ?2f" "fmovdvs %xcc, ?1f, ?2f")
  (PARALLEL
   (SET (REG F64 (HOLE 2 FREG))
	(IFTHENELSE F64 (REG I1 xcc_v)
		    (REG F64 (HOLE 1 FREG))
		    (REG F64 (HOLE 2 FREG))))
   )
  )

;; == Move Always ==
;; fmov{s,d,q}a %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsa ??1D, ??2F, ??3F" "fmovsa ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (INTCONST I1 1)
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovda ??1D, ?2f, ?3f" "fmovda ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (INTCONST I1 1)
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move Never ==
;; fmov{s,d,q}n %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsn ??1D, ??2F, ??3F" "fmovsn ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (INTCONST I1 0)
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdn ??1D, ?2f, ?3f" "fmovdn ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (INTCONST I1 0)
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Unordered ==
;; fmov{s,d,q}u %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsu ??1D, ??2F, ??3F" "fmovsu ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdu ??1D, ?2f, ?3f" "fmovdu ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Greater ==
;; fmov{s,d,q}g %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsg ??1D, ??2F, ??3F" "fmovsg ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdg ??1D, ?2f, ?3f" "fmovdg ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Unordered or Greater ==
;; fmov{s,d,q}ug %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsug ??1D, ??2F, ??3F" "fmovsug ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdug ??1D, ?2f, ?3f" "fmovdug ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Less ==
;; fmov{s,d,q}l %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsl ??1D, ??2F, ??3F" "fmovsl ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdl ??1D, ?2f, ?3f" "fmovdl ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Unordered or Less ==
;; fmov{s,d,q}ul %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsul ??1D, ??2F, ??3F" "fmovsul ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdul ??1D, ?2f, ?3f" "fmovdul ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Less or Greater ==
;; fmov{s,d,q}lg %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovslg ??1D, ??2F, ??3F" "fmovslg ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdlg ??1D, ?2f, ?3f" "fmovdlg ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Not Equal ==
;; fmov{s,d,q}ne %fccn, freg, freg (synonyms: fmov{s,d,q}nz)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsne ??1D, ??2F, ??3F" "fmovsne ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (TSTNE I1 (HOLE 1) (INTCONST I2 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdne ??1D, ?2f, ?3f" "fmovdne ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (TSTNE I1 (HOLE 1) (INTCONST I2 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Equal ==
;; fmov{s,d,q}e %fccn, freg, freg (synonyms: fmov{s,d,q}z)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovse ??1D, ??2F, ??3F" "fmovse ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovde ??1D, ?2f, ?3f" "fmovde ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Unordered or Equal ==
;; fmov{s,d,q}ue %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsue ??1D, ??2F, ??3F" "fmovsue ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdue ??1D, ?2f, ?3f" "fmovdue ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Greater or Equal ==
;; fmov{s,d,q}ge %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsge ??1D, ??2F, ??3F" "fmovsge ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdge ??1D, ?2f, ?3f" "fmovdge ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Unordered or Greater or Equal ==
;; fmov{s,d,q}uge %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsuge ??1D, ??2F, ??3F" "fmovsuge ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
				  (TSTEQ I1 (HOLE 1) (INTCONST I2 3))))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovduge ??1D, ?2f, ?3f" "fmovduge ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
				  (TSTEQ I1 (HOLE 1) (INTCONST I2 3))))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Less or Equal
;; fmov{s,d,q}le %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsle ??1D, ??2F, ??3F" "fmovsle ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 1)))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdle ??1D, ?2f, ?3f" "fmovdle ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 1)))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Unordered or Less or Equal ==
;; fmov{s,d,q}ule %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovsule ??1D, ??2F, ??3F" "fmovsule ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
				  (TSTEQ I1 (HOLE 1) (INTCONST I2 3))))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdule ??1D, ?2f, ?3f" "fmovdule ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
				  (TSTEQ I1 (HOLE 1) (INTCONST I2 3))))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Ordered ==
;; fmov{s,d,q}o %fccn, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovso ??1D, ??2F, ??3F" "fmovso ??1D, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32 (TSTNE I1 (HOLE 1) (INTCONST I2 3))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovdo ??1D, ?2f, ?3f" "fmovdo ??1D, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64 (TSTNE I1 (HOLE 1) (INTCONST I2 3))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Move F-P Register on Integer Register Condition (FMOVr)
;;;
;;;	FMOVRZ	Move if Register Zero
;;;	FMOVRLEZ Move if Register Less Than or Equal to Zero
;;;	FMOVRLZ	Move if Register Less Than Zero
;;;	FMOVRNZ	Move if Register Not Zero
;;;	FMOVRGZ	Move if Register Greater Than Zero
;;;	FMOVRGEZ Move if Register Greater Than or Equal to Zero
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Move if Register Zero ==
;; fmovr{s,d,q}e reg, freg, freg (synonym: fmovr{s,d,q}z)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovrse ?1r, ??2F, ??3F" "fmovrse ?1r, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32
		    (TSTEQ I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovrde ?1r, ?2f, ?3f" "fmovrde ?1r, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64
		    (TSTEQ I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Register Less Than or Equal to Zero ==
;; fmovr{s,d,q}lez reg, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovrslez ?1r, ??2F, ??3F" "fmovrslez ?1r, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32
		    (TSTLES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovrdlez ?1r, ?2f, ?3f" "fmovrdlez ?1r, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64
		    (TSTLES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Register Less Than Zero ==
;; fmovr{s,d,q}lz reg, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovrslz ?1r, ??2F, ??3F" "fmovrslz ?1r, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32
		    (TSTLTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovrdlz ?1r, ?2f, ?3f" "fmovrdlz ?1r, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64
		    (TSTLTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Register Not Zero ==
;; fmovr{s,d,q}ne reg, freg, freg (synonym: fmovr{s,d,q}nz)
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovrsne ?1r, ??2F, ??3F" "fmovrsne ?1r, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32
		    (TSTNE I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovrdne ?1r, ?2f, ?3f" "fmovrdne ?1r, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64
		    (TSTNE I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Register Greater Than Zero ==
;; fmovr{s,d,q}gz reg, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovrsgz ?1r, ??2F, ??3F" "fmovrsgz ?1r, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32
		    (TSTGTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovrdgz ?1r, ?2f, ?3f" "fmovrdgz ?1r, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64
		    (TSTGTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )

;; == Move if Register Greater Than or Equal to Zero ==
;; fmovr{s,d,q}gez reg, freg, freg
;; *** Quad Floating-Pointは未サポート ***
(DEFINST ("fmovrsgez ?1r, ??2F, ??3F" "fmovrsgez ?1r, ??2F, ??3F")
  (PARALLEL
   (SET (HOLE 3)
	(IFTHENELSE F32
		    (TSTGES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (HOLE 2)
		    (HOLE 3)))
   )
  )

(DEFINST ("fmovrdgez ?1r, ?2f, ?3f" "fmovrdgez ?1r, ?2f, ?3f")
  (PARALLEL
   (SET (REG F64 (HOLE 3 FREG))
	(IFTHENELSE F64
		    (TSTGES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (REG F64 (HOLE 2 FREG))
		    (REG F64 (HOLE 3 FREG))))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Move Integer Register on Condition (MOVcc)
;;;
;;;	MOVA	Move Always
;;;	MOVN	Move Never
;;;	MOVNE	Move if Not Equal
;;;	MOVE	Move if Equal
;;;	MOVG	Move if Greater
;;;	MOVLE	Move if Less or Equal
;;;	MOVGE	Move if Greater or Equal
;;;	MOVL	Move if Less
;;;	MOVGU	Move if Greater Unsigned
;;;	MOVLEU	Move if Less or Equal Unsigned
;;;	MOVCC	Move if Carry Clear (Greater or Equal, Unsigned)
;;;	MOVCS	Move if Carry Set (Less than, Unsigned)
;;;	MOVPOS	Move if Positive
;;;	MOVNEG	Move if Negative
;;;	MOVVC	Move if Overflow Clear
;;;	MOVVS	Move if Overflow Set
;;;
;;;	MOVFA	Move Always
;;;	MOVFN	Move Never
;;;	MOVFU	Move if Unordered
;;;	MOVFG	Move if Greater
;;;	MOVFUG	Move if Unordered or Greater
;;;	MOVFL	Move if Less
;;;	MOVFUL	Move if Unordered or Less
;;;	MOVFLG	Move if Less or Greater
;;;	MOVFNE	Move if Not Equal
;;;	MOVFE	Move if Equal
;;;	MOVFUE	Move if Unordered or Equal
;;;	MOVFGE	Move if Greater or Equal
;;;	MOVFUGE	Move if Unordered or Greater or Equal
;;;	MOVFLE	Move if Less or Equal
;;;	MOVFULE	Move if Unordered or Less or Equal
;;;	MOVFO	Move if Ordered
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Move Always ==
;; mova i_or_x_cc, reg_or_imm11, reg
(DEFINST ("mova %icc, ??1V, ?2r" "mova %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (INTCONST I1 1)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("mova %xcc, ??1V, ?2r" "mova %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (INTCONST I1 1)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move Never ==
;; movn i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movn %icc, ??1V, ?2r" "movn %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (INTCONST I1 0)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movn %xcc, ??1V, ?2r" "movn %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (INTCONST I1 0)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Not Equal ==
;; movne i_or_x_cc, reg_or_imm11, reg (synonym: movnz)
(DEFINST ("movne %icc, ??1V, ?2r" "movne %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 icc_z))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movne %xcc, ??1V, ?2r" "movne %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 xcc_z))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Equal ==
;; move i_or_x_cc, reg_or_imm11, reg (synonym: movz)
(DEFINST ("move %icc, ??1V, ?2r" "move %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 icc_z)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("move %xcc, ??1V, ?2r" "move %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 xcc_z)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Greater ==
;; movg i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movg %icc, ??1V, ?2r" "movg %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (BOR I1 (REG I1 icc_z)
				      (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movg %xcc, ??1V, ?2r" "movg %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (BOR I1 (REG I1 xcc_z)
				      (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Less or Equal ==
;; movle i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movle %icc, ??1V, ?2r" "movle %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BOR I1 (REG I1 icc_z)
			     (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movle %xcc, ??1V, ?2r" "movle %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BOR I1 (REG I1 xcc_z)
			     (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Greater or Equal ==
;; movge i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movge %icc, ??1V, ?2r" "movge %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movge %xcc, ??1V, ?2r" "movge %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v)))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Less ==
;; movl i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movl %icc, ??1V, ?2r" "movl %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movl %xcc, ??1V, ?2r" "movl %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BXOR I1 (REG I1 xcc_n) (REG I1 xcc_v))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Greater Unsigned ==
;; movgu i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movgu %icc, ??1V, ?2r" "movgu %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (BOR I1 (REG I1 icc_c) (REG I1 icc_z)))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movgu %xcc, ??1V, ?2r" "movgu %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z)))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Less or Equal Unsigned ==
;; movleu i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movleu %icc, ??1V, ?2r" "movleu %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BOR I1 (REG I1 icc_c) (REG I1 icc_z))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movleu %xcc, ??1V, ?2r" "movleu %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BOR I1 (REG I1 xcc_c) (REG I1 xcc_z))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Carry Clear (Greater or Equal, Unsigned) ==
;; movcc i_or_x_cc, reg_or_imm11, reg (synonym: movgeu)
(DEFINST ("movcc %icc, ??1V, ?2r" "movcc %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 icc_c))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movcc %xcc, ??1V, ?2r" "movcc %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 xcc_c))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Carry Set (Less than, Unsigned) ==
;; movcs i_or_x_cc, reg_or_imm11, reg (synonym: movlu)
(DEFINST ("movcs %icc, ??1V, ?2r" "movcs %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 icc_c)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movcs %xcc, ??1V, ?2r" "movcs %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 xcc_c)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Positive ==
;; movpos i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movpos %icc, ??1V, ?2r" "movpos %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 icc_n))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movpos %xcc, ??1V, ?2r" "movpos %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 xcc_n))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Negative ==
;; movneg i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movneg %icc, ??1V, ?2r" "movneg %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 icc_n)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movneg %xcc, ??1V, ?2r" "movneg %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 xcc_n)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Overflow Clear ==
;; movvc i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movvc %icc, ??1V, ?2r" "movvc %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 icc_v))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movvc %xcc, ??1V, ?2r" "movvc %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (BNOT I1 (REG I1 xcc_v))
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

;; == Move if Overflow Set ==
;; movvs i_or_x_cc, reg_or_imm11, reg
(DEFINST ("movvs %icc, ??1V, ?2r" "movvs %icc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 icc_v)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )

(DEFINST ("movvs %xcc, ??1V, ?2r" "movvs %xcc, ??1V, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG))
	(IFTHENELSE I64 (REG I1 xcc_v)
		    (HOLE 1)
		    (REG I64 (HOLE 2 IREG))))
   )
  )


;; == Move Always ==
;; mova %fccn, reg_or_imm11, reg
(DEFINST ("mova ??1D, ??2V, ?3r" "mova ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (INTCONST I1 1)
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move Never ==
;; movn %fccn, reg_or_imm11, reg
(DEFINST ("movn ??1D, ??2V, ?3r" "movn ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (INTCONST I1 0)
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Unordered ==
;; movu %fccn, reg_or_imm11, reg
(DEFINST ("movu ??1D, ??2V, ?3r" "movu ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (TSTEQ I1 (HOLE 1) (INTCONST I2 3))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )


;; == Move if Greater ==
;; movg %fccn, reg_or_imm11, reg
(DEFINST ("movg ??1D, ??2V, ?3r" "movg ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Unordered or Greater ==
;; movug %fccn, reg_or_imm11, reg
(DEFINST ("movug ??1D, ??2V, ?3r" "movug ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Less ==
;; movl %fccn, reg_or_imm11, reg
(DEFINST ("movl ??1D, ??2V, ?3r" "movl ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Unordered or Less ==
;; movul %fccn, reg_or_imm11, reg
(DEFINST ("movul ??1D, ??2V, ?3r" "movul ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Less or Greater ==
;; movlg %fccn, reg_or_imm11, reg
(DEFINST ("movlg ??1D, ??2V, ?3r" "movlg ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Not Equal ==
;; movne %fccn, reg_or_imm11, reg (synonym: movnz)
(DEFINST ("movne ??1D, ??2V, ?3r" "movne ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (TSTNE I1 (HOLE 1) (INTCONST I2 0))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Equal ==
;; move %fccn, reg_or_imm11, reg (synonym: movz)
(DEFINST ("move ??1D, ??2V, ?3r" "move ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Unordered or Equal ==
;; movue %fccn, reg_or_imm11, reg
(DEFINST ("movue ??1D, ??2V, ?3r" "movue ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 3)))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Greater or Equal ==
;; movge %fccn, reg_or_imm11, reg
(DEFINST ("movge ??1D, ??2V, ?3r" "movge ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 2)))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Unordered or Greater or Equal ==
;; movuge %fccn, reg_or_imm11, reg
(DEFINST ("movuge ??1D, ??2V, ?3r" "movuge ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 2))
				  (TSTEQ I1 (HOLE 1) (INTCONST I2 3))))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Less or Equal ==
;; movle %fccn, reg_or_imm11, reg
(DEFINST ("movle ??1D, ??2V, ?3r" "movle ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (TSTEQ I1 (HOLE 1) (INTCONST I2 1)))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Unordered or Less or Equal ==
;; movule %fccn, reg_or_imm11, reg
(DEFINST ("movule ??1D, ??2V, ?3r" "movule ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 0))
			     (BOR I1 (TSTEQ I1 (HOLE 1) (INTCONST I2 1))
				  (TSTEQ I1 (HOLE 1) (INTCONST I2 3))))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )

;; == Move if Ordered ==
;; movo %fccn, reg_or_imm11, reg
(DEFINST ("movo ??1D, ??2V, ?3r" "movo ??1D, ??2V, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64 (TSTNE I1 (HOLE 1) (INTCONST I2 3))
		    (HOLE 2)
		    (REG I64 (HOLE 3 IREG))))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Move Integer Register on Register Condition (MOVR)
;;;
;;;	MOVRZ	Move if Register Zero
;;;	MOVRLEZ	Move if Register Less Than or Equal to Zero
;;;	MOVRLZ	Move if Register Less Than Zero
;;;	MOVRNZ	Move if Register Not Zero
;;;	MOVRGZ	Move if Register Greater Than Zero
;;;	MOVRGEZ	Move if Register Greater Than or Equal to Zero
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Move if Register Zero ==
;; movrz reg, reg_or_imm10, reg (synonym: movre)
(DEFINST ("movrz ?1r, ??2T, ?3r" "movrz ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTEQ I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (CONVZX I64 (HOLE 2))
		    (REG I64 (HOLE 3 IREG_D))))
   )
  )

;; == Move if Register Less Than or Equal to Zero ==
;; movrlez reg, reg_or_imm10, reg
(DEFINST ("movrlez ?1r, ??2T, ?3r" "movrlez ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTLES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (CONVZX I64 (HOLE 2))
		    (REG I64 (HOLE 3 IREG_D))))
   )
  )

;; == Move if Register Less Than Zero ==
;; movrlz reg, reg_or_imm10, reg
(DEFINST ("movrlz ?1r, ??2T, ?3r" "movrlz ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTLTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (CONVZX I64 (HOLE 2))
		    (REG I64 (HOLE 3 IREG_D))))
   )
  )

;; == Move if Register Not Zero ==
;; movrnz reg, reg_or_imm10, reg (synonym: movrne)
(DEFINST ("movrnz ?1r, ??2T, ?3r" "movrnz ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTNE I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (CONVZX I64 (HOLE 2))
		    (REG I64 (HOLE 3 IREG_D))))
   )
  )

;; == Move if Register Greater Than Zero ==
;; movrgz reg, reg_or_imm10, reg
(DEFINST ("movrgz ?1r, ??2T, ?3r" "movrgz ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTGTS I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (CONVZX I64 (HOLE 2))
		    (REG I64 (HOLE 3 IREG_D))))
   )
  )

;; == Move if Register Greater Than or Equal to Zero ==
;; movrgez reg, reg_or_imm10, reg
(DEFINST ("movrgez ?1r, ??2T, ?3r" "movrgez ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(IFTHENELSE I64
		    (TSTGES I1 (REG I64 (HOLE 1 IREG)) (INTCONST I64 0))
		    (CONVZX I64 (HOLE 2))
		    (REG I64 (HOLE 3 IREG_D))))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Multiply and Divide (64-bit)
;;;
;;;	MULX	Multiply (signed or unsigned)
;;;	SDIVX	Signed Divide
;;;	UDIVX	Unsigned Divide
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Multiply (signed or unsigned) ==
;; mulx reg, reg_or_imm, reg
(DEFINST ("mulx ?1r, ??2R, ?3r" "umulx ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(MUL I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Signed Divide ==
;; sdivx reg, reg_or_imm, reg
(DEFINST ("sdivx ?1r, ??2R, ?3r" "sdivx ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(DIVS I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Unsigned Divide ==
;; udivx reg, reg_or_imm, reg
(DEFINST ("udivx ?1r, ??2R, ?3r" "udivx ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(DIVU I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Multiply (32-bit)
;;;
;;; *** Deprecated ***
;;;
;;;	UMUL	Unsigned Integer Multiply
;;;	SMUL	Signed Integer Multiply
;;;	UMULcc	Unsigned Integer Multiply and modify cc's
;;;	SMULcc	Signed Integer Multiply and modify cc's
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Unsigned Integer Multiply ==
;; umul reg, reg_or_imm, reg
(DEFINST ("umul ?1r, ??2R, ?3r" "umul ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
	     (CONVZX I64 (CONVIT I32 (HOLE 2)))))
   (SET (REG I64 Y)
	(RSHU I64 
	      (MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVZX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   )
  )

;; destinationがg0の場合はYレジスタのみ変更される
(DEFINST ("umul ?1r, ??2R, %g0" "umul ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I64 Y)
	(RSHU I64 
	      (MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVZX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   )
  )

;; == Signed Integer Multiply ==
;; smul reg, reg_or_imm, reg
(DEFINST ("smul ?1r, ??2R, ?3r" "smul ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
	     (CONVSX I64 (CONVIT I32 (HOLE 2)))))
   (SET (REG I64 Y)
	(RSHU I64
	      (MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVSX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   )
  )

;; destinationがg0の場合はYレジスタのみ変更される
(DEFINST ("smul ?1r, ??2R, %g0" "smul ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I64 Y)
	(RSHU I64
	      (MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVSX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   )
  )

;; == Unsigned Integer Multiply and modify icc ==
;; umulcc reg, reg_or_imm, reg
(DEFINST ("umulcc ?1r, ??2R, ?3r" "umulcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
	     (CONVZX I64 (CONVIT I32 (HOLE 2)))))
   (SET (REG I64 Y)
	(RSHU I64 
	      (MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVZX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 
		(CONVIT I32
			(MUL I64
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			     (CONVZX I64 (CONVIT I32 (HOLE 2)))))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	       (CONVIT I32
		       (MUL I64
			    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			    (CONVZX I64 (CONVIT I32 (HOLE 2)))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 
		(MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		     (CONVZX I64 (CONVIT I32 (HOLE 2))))
		(INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	       (MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		    (CONVZX I64 (CONVIT I32 (HOLE 2))))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はY、フラグのみ設定する
(DEFINST ("umulcc ?1r, ??2R, %g0" "umulcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I64 Y)
	(RSHU I64 
	      (MUL I64 (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVZX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 
		(CONVIT I32
			(MUL I64
			     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			     (CONVZX I64 (CONVIT I32 (HOLE 2)))))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	       (CONVIT I32
		       (MUL I64
			    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			    (CONVZX I64 (CONVIT I32 (HOLE 2)))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 
		(MUL I64
		     (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		     (CONVZX I64 (CONVIT I32 (HOLE 2))))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	       (MUL I64
		    (CONVZX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		    (CONVZX I64 (CONVIT I32 (HOLE 2))))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; == Signed Integer Multiply and modify icc ==
;; smulcc reg, reg_or_imm, reg
(DEFINST ("smulcc ?1r, ??2R, ?3r" "smulcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
	     (CONVSX I64 (CONVIT I32 (HOLE 2)))))
   (SET (REG I64 Y)
	(RSHU I64
	      (MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVSX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   (SET (REG I1 icc_n)
	(TSTLTS I1
		(CONVIT I32
			(MUL I64
			     (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			     (CONVSX I64 (CONVIT I32 (HOLE 2)))))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	       (CONVIT I32
		       (MUL I64
			    (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			    (CONVSX I64 (CONVIT I32 (HOLE 2)))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1
		(MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		     (CONVSX I64 (CONVIT I32 (HOLE 2))))
		(INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	       (MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		    (CONVSX I64 (CONVIT I32 (HOLE 2))))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )

;; destinationがg0の場合はY、フラグのみ設定する
(DEFINST ("smulcc ?1r, ??2R, %g0" "smulcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I64 Y)
	(RSHU I64
	      (MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		   (CONVSX I64 (CONVIT I32 (HOLE 2))))
	      (INTCONST I32 32)))
   (SET (REG I1 icc_n)
	(TSTLTS I1
		(CONVIT I32
			(MUL I64
			     (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			     (CONVSX I64 (CONVIT I32 (HOLE 2)))))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1
	       (CONVIT I32
		       (MUL I64
			    (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
			    (CONVSX I64 (CONVIT I32 (HOLE 2)))))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v) (INTCONST I1 0))
   (SET (REG I1 icc_c) (INTCONST I1 0))
   (SET (REG I1 xcc_n)
	(TSTLTS I1
	       (MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		    (CONVSX I64 (CONVIT I32 (HOLE 2))))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1
	       (MUL I64 (CONVSX I64 (CONVIT I32 (REG I64 (HOLE 1 IREG))))
		    (CONVSX I64 (CONVIT I32 (HOLE 2))))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v) (INTCONST I1 0))
   (SET (REG I1 xcc_c) (INTCONST I1 0))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Multiply Step
;;;
;;; *** Deprecated ***
;;;
;;;	MULScc	Multiply Step and modify cc's
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Multiply Step and modify icc ==
;; mulscc reg, reg_or_imm, reg
(DEFINST ("mulscc ?1r, ??2R, ?3r" "mulscc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(CONVZX I64
		(ADD I32
		     (BOR I32
			  (LSH I32
			   (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
			   (INTCONST I32 31))
			  (RSHS I32
			   (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			   (INTCONST I32 1)))
		     (IFTHENELSE I32
				 (TSTEQ I1
				  (BAND I64 (REG I64 Y) (INTCONST I64 1))
				  (INTCONST I64 1))
				 (CONVIT I32 (HOLE 2))
				 (INTCONST I32 0)))))
   (SET (REG I64 Y)
	(CONVZX I64
		(BOR I32 (LSH I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			      (INTCONST I32 31))
		     (RSHU I32 (CONVIT I32 (REG I64 Y)) (INTCONST I32 1)))))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (ADD I32
		     (BOR I32
		      (LSH I32
		       (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		       (INTCONST I32 31))
		      (RSHS I32
		       (CONVIT I32 (REG I64 (HOLE 1 IREG))) (INTCONST I32 1)))
		     (IFTHENELSE I32
				 (TSTEQ I1
				  (BAND I64 (REG I64 Y) (INTCONST I64 1))
				  (INTCONST I64 1))
				 (CONVIT I32 (HOLE 2))
				 (INTCONST I32 0)))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (ADD I32
		   (BOR I32
		    (LSH I32
		     (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		     (INTCONST I32 31))
		    (RSHS I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			  (INTCONST I32 1)))
		   (IFTHENELSE I32
			       (TSTEQ I1
				(BAND I64 (REG I64 Y) (INTCONST I64 1))
				(INTCONST I64 1))
			       (CONVIT I32 (HOLE 2))
			       (INTCONST I32 0)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (BOR I32
		      (LSH I32
		       (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		       (INTCONST I32 31))
		      (RSHS I32
		       (CONVIT I32 (REG I64 (HOLE 1 IREG))) (INTCONST I32 1)))
		  (IFTHENELSE I32
			      (TSTEQ I1 (BAND I64 (REG I64 Y) (INTCONST I64 1))
				     (INTCONST I64 1))
			      (CONVIT I32 (HOLE 2))
			      (INTCONST I32 0))
		  (INTCONST I1 0)))
   (SET (REG I1 icc_c) 
	(CARRY I1 (BOR I32
		   (LSH I32
		    (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		    (INTCONST I32 31))
		   (RSHS I32
	            (CONVIT I32 (REG I64 (HOLE 1 IREG))) (INTCONST I32 1)))
	       (IFTHENELSE I32
			   (TSTEQ I1
			    (BAND I64 (REG I64 Y) (INTCONST I64 1))
			    (INTCONST I64 1))
			   (CONVIT I32 (HOLE 2))
			   (INTCONST I32 0))
	       (INTCONST I1 0)))
   )
  )
	
;; destinationがg0の場合はY、フラグのみ設定する
(DEFINST ("mulscc ?1r, ??2R, %g0" "mulscc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I64 Y)
	(CONVZX I64
	 (BOR I32 (LSH I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (INTCONST I32 31))
	      (RSHU I32 (CONVIT I32 (REG I64 Y)) (INTCONST I32 1)))))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (ADD I32
		    (BOR I32
		     (LSH I32
		      (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		      (INTCONST I32 31))
		     (RSHS I32
		      (CONVIT I32 (REG I64 (HOLE 1 IREG))) (INTCONST I32 1)))
		    (IFTHENELSE I32
				(TSTEQ I1
				 (BAND I64 (REG I64 Y) (INTCONST I64 1))
				 (INTCONST I64 1))
				(CONVIT I32 (HOLE 2))
				(INTCONST I32 0)))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (ADD I32
		   (BOR I32
		    (LSH I32
		     (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		     (INTCONST I32 31))
		    (RSHS I32
		     (CONVIT I32 (REG I64 (HOLE 1 IREG))) (INTCONST I32 1)))
		   (IFTHENELSE I32
			       (TSTEQ I1
			        (BAND I64 (REG I64 Y) (INTCONST I64 1))
				(INTCONST I64 1))
			       (CONVIT I32 (HOLE 2))
			       (INTCONST I32 0)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (BOR I32
		      (LSH I32
		       (CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
		       (INTCONST I32 31))
		      (RSHS I32
		       (CONVIT I32 (REG I64 (HOLE 1 IREG))) (INTCONST I32 1)))
		  (IFTHENELSE I32
			      (TSTEQ I1 (BAND I64 (REG I64 Y) (INTCONST I64 1))
				     (INTCONST I64 1))
			      (CONVIT I32 (HOLE 2))
			      (INTCONST I32 0))
		  (INTCONST I1 0)))
   (SET (REG I1 icc_c) 
	(CARRY I1 (BOR I32
		       (LSH I32
			(CONVZX I32 (BXOR I1 (REG I1 icc_n) (REG I1 icc_v)))
			(INTCONST I32 31))
		       (RSHS I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			     (INTCONST I32 1)))
	       (IFTHENELSE I32
			   (TSTEQ I1 (BAND I64 (REG I64 Y) (INTCONST I64 1))
				  (INTCONST I64 1))
			   (CONVIT I32 (HOLE 2))
			   (INTCONST I32 0))
	       (INTCONST I1 0)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; No Operation
;;;
;;;	NOP	No Operation
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == NOP Instruction ==
;; nop
(DEFINST ("nop" "nop")
  (PARALLEL
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Population Count
;;;
;;;	POPC	Population Count
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Population Count ==
;; popc reg_or_imm, reg
;; /// ループでアルゴリズム記述しないと難しい ///
;; *** popcは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Prefetch Data
;;;
;;;	PREFETCH	Prefetch Data
;;;	PREFETCHA	Prefetch Data from Alternate Space
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Prefetch Data ==
;; prefetch [address], prefetch_fcn
;; *** Prefetch Data関連命令は未サポート ***

;; == Prefetch Data from Alternate Space ==
;; prefetcha [regaddr] imm_asi, prefetch_fcn
;; *** Prefetch Data関連命令は未サポート ***

;; == Prefetch Data from Alternate Space ==
;; prefetcha [reg_plus_imm] %asi, prefetch_fcn
;; *** Prefetch Data関連命令は未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Read Privileged Register
;;;
;;;	RDPR	Read Privileged Register
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Read Privileged Register ==
;; rdpr %tpc, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %tnpc, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %tstate, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %tt, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %tick, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %tba, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %pstate, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %tl, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %pil, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %cwp, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %cansave, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %canrestore, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %cleanwin, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %otherwin, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %wstate, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %fq, reg
;; *** Privileged Registerは未サポート ***

;; == Read Privileged Register ==
;; rdpr %ver, reg
;; *** Privileged Registerは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Read State Register
;;;
;;;	RDY	Read Y Register *** Deprecated ***
;;;	RDCCR	Read Condition Codes Register
;;;	RDASI	Read ASI Register
;;;	RDTICK	Read Tick Register
;;;	RDPC	Read Program Counter
;;;	RDFPRS	Read Floating-Point Registers Status Register
;;;	RDASR	Read Ancillary State Register (reserved)
;;;	RDASR	Implementation-dependent (impl. dep. #47)
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Read Y Register ==
;; rd %y, reg
(DEFINST ("rd %y, ?1r" "rd %y, ?1r")
  (PARALLEL
   (SET (REG I64 (HOLE 1 IREG_D)) (REG I64 Y))
   )
  )

;; == Read Condition Codes Register ==
;; rd %ccr, reg
;; *** %ccrは未サポート ***

;; == Read ASI Register ==
;; rd %asi, reg
;; *** %asiは未サポート ***

;; == Read Tick Register ==
;; rd %tick, reg
;; *** %tickは未サポート ***

;; == Read Program Counter ==
;; rd %pc, reg
(DEFINST ("rd %pc, ?1r" "rd %pc, ?1r")
  (PARALLEL
   (SET (REG I64 (HOLE 1 IREG_D)) (REG I64 PC))
   )
  )

;; == Read Floating-Point Registers Status Register ==
;; rd %fprs, reg
;; *** %fprsは未サポート ***

;; == Read Ancillary State Register (reserved) ==
;; rd asr_reg, reg
;; ** ASRは未サポート **


;;;----------------------------------------------------------------------
;;;
;;; RETURN
;;;
;;;	RETURN	RETURN
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == RETURN ==
;; return address
;; *** Register Windowは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; SAVE and RESTORE
;;;
;;;	SAVE	Save caller's window
;;;	RESTORE	Restore caller's window
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;;
;; == Save caller's window ==
;; save reg, reg_or_imm, reg
;; *** Register Windowは未サポート ***
;;(DEFINST "save reg, reg_or_imm, reg")

;;
;; == Restore caller's window ==
;; restore reg, reg_or_imm, reg
;; *** Register Windowは未サポート ***
;;(DEFINST "restore reg, reg_or_imm, reg")


;;;----------------------------------------------------------------------
;;;
;;; SAVED and RESTORED
;;;
;;;	SAVED	Window has been Saved
;;;	RESTORED Window has been Restored
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Window has been Saved ==
;; saved
;; *** Register Windowは未サポート ***

;; == Window has been Restored ==
;; restored
;; *** Register Windowは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; SETHI
;;;
;;;	SETHI	Set High 22 Bits of Low Word
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Set High-Order 22 bits ==
;; sethi imm22, reg
(DEFINST ("sethi ?1h, ?2r" "sethi ?1h, ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(CONVZX I64 (LSH I32 (CONVSX I32 (INTCONST I22 (HOLE 1)))
			 (INTCONST I32 10))))
   )
  )

;; == Set High-Order 22 bits ==
;; sethi %hi(imm32), reg
;;(DEFINST ("sethi %hi(?1I), ?2r" "sethi %hi(?1I), ?2r")
;;  (PARALLEL
;;   (SET (REG I64 (HOLE 2 IREG_D))
;;	(CONVZX I64 (BAND I32 (INTCONST I32 (HOLE 1))
;;                        (INTCONST I32 #xfffffc00)))
;;   )
;;  )

;; sethi %hi(imm32), reg
;; == Set High-Order 22 bits ==
;; sethi %hi(imm32), reg
;;(DEFINST ("sethi %hi(?1a), ?2r" "sethi %hi(?1a), ?2r")
;;  (PARALLEL
;;   (SET (REG I64 (HOLE 2 IREG_D))
;;	(BAND I64 (ASMCONST I64 (HOLE 1)) (INTCONST I64 #x00000000fffffc00))))
;;   )
;;  )
(DEFINST ("sethi %hi(?1l), ?2r" "sethi %hi(?1l), ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D))
	(BAND I64 (ASMCONST I64 (LABEL I64 (HOLE 1)))
	      (INTCONST I64 #x00000000fffffc00)))
   )
  )

(DEFINST ("sethi %hi(?1l+?2i), ?3r" "sethi %hi(?1l+?2i), ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BAND I64 (ASMCONST I64 (ADD I64 (LABEL I64 (HOLE 1))
				     (INTCONST I64 (HOLE 2))))
	      (INTCONST I64 #x00000000fffffc00)))
   )
  )

(DEFINST ("sethi %hi(?1l-?2i), ?3r" "sethi %hi(?1l-?2i), ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BAND I64 (ASMCONST I64 (SUB I64 (LABEL I64 (HOLE 1))
				     (INTCONST I64 (HOLE 2))))
	      (INTCONST I64 #x00000000fffffc00)))
   )
  )

(DEFINST ("sethi %hi(?1l-?2l), ?3r" "sethi %hi(?1l-?2l), ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(BAND I64 (ASMCONST I64 (SUB I64 (LABEL I64 (HOLE 1))
				     (LABEL I64 (HOLE 2))))
	      (INTCONST I64 #x00000000fffffc00)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Shift
;;;
;;;	SLL	Shift Left Logical - 32 Bits
;;;	SRL	Shift Right Logical - 32 Bits
;;;	SRA	Shift Right Arithmetic - 32 Bits
;;;	SLLX	Shift Left Logical - 64 Bits
;;;	SRLX	Shift Right Logical - 64 Bits
;;;	SRAX	Shift Right Arithmetic - 64 Bits
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Shift Left Logical ==
;; sll reg, reg_or_imm, reg
(DEFINST ("sll ?1r, ??2S, ?3r" "sll ?1r, ??2S, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(LSH I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Shift Right Logical ==
;; srl reg, reg_or_imm, reg
(DEFINST ("srl ?1r, ??2S, ?3r" "srl ?1r, ??2S, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(CONVZX I64 (RSHU I32 (CONVIT I32 (REG I64 (HOLE 1 IREG))) (HOLE 2))))
   )
  )

;; == Shift Right Arithmetic ==
;; sra reg, reg_or_imm, reg
(DEFINST ("sra ?1r, ??2S, ?3r" "sra ?1r, ??2S, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(CONVSX I64 (RSHS I32 (CONVIT I32 (REG I64 (HOLE 1 IREG))) (HOLE 2))))
   )
  )

;; == Shift Left Logical -- 64 Bits ==
;; sllx reg, reg_or_imm, reg
(DEFINST ("sllx ?1r, ??2T, ?3r" "sllx ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(LSH I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Shift Right Logical -- 64 Bits ==
;; srlx reg, reg_or_imm, reg
(DEFINST ("srlx ?1r, ??2T, ?3r" "srlx ?1r, ??2T, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(RSHU I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Shift Right Arithmetic -- 64 Bits ==
;; srax reg, reg_or_imm, reg
(DEFINST ("srax ?1r, ??2S, ?3r" "srax ?1r, ??2S, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(RSHS I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Software-Initiated Reset
;;;
;;;	SIR	Software-initiated reset
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Software-Initiated Reset ==
;; sir simm13
;; *** Software-Initiated Resetは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Store Barrier
;;;
;;;	STBAR	Store Barrier
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Store Barrier ==
;; stbar
;; *** STBAR Instructionは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Store Floating-Point
;;;
;;;	STF	Store Floating-Point Register
;;;	STDF	Double Floating-Point Register
;;;	STQF	Quad Floating-Point Register
;;;	STFSR	Store Floating-Point State Register Lower *** Deprecated ***
;;;	STXFSR	Store Floating-Point State Register
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Store Floating-point ==
;; st freg, [address]
(DEFINST ("st ??1F, [??2A]" "st ??1F, [??2A]")
  (PARALLEL
   (SET (MEM F32 (HOLE 2)) (HOLE 1))
   )
  )

;; == Store Double Floating-point ==
;; std freg, [address]
(DEFINST ("std ?1f, [??2A]" "std ?1f, [??2A]")
  (PARALLEL
   (SET (MEM F64 (HOLE 2)) (REG F64 (HOLE 1 FREG)))
   )
  )

;; == Quad Floating-Point Register ==
;; stq freg, [address]
;; *** Quad Floating-Pointは未サポート ***

;; == Store Floating-point State Register Lower ==
;; st %fsr, [address]
;; *** %fsrは未サポート ***

;; == Store Floating-point State Register ==
;; stx %fsr, [address]
;; *** %fsrは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Store Floating-Point into Alternate Space
;;;
;;;	STFA	Store Floating-Point Register to Alternate Space
;;;	STDFA	Store Double Floating-Point Register to Alternate Space
;;;	STQFA	Store Quad Floating-Point Register to Alternate Space
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Store Floating-Point Register to Alternate Space ==
;; sta freg, [regaddr] imm_asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Floating-Point Register to Alternate Space ==
;; sta freg, [reg_plus_imm] %asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Double Floating-Point Register to Alternate Space ==
;; stda freg, [regaddr] imm_asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Double Floating-Point Register to Alternate Space ==
;; stda freg, [reg_plus_imm] %asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Quad Floating-Point Register to Alternate Space ==
;; stqa freg, [regaddr] imm_asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Quad Floating-Point Register to Alternate Space ==
;; stqa freg, [reg_plus_imm] %asi
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Store Integer
;;;
;;;	STB	Store Byte
;;;	STH	Store Halfword
;;;	STW	Store Word
;;;	STX	Store Extended Word
;;;	STD	Store Doubleword *** Deprecated ***
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Store Byte ==
;; stb reg, [address]
(DEFINST ("stb ?1r, [??2A]" "stb ?1r, [??2A]")
  (PARALLEL
   (SET (MEM I8 (HOLE 2)) (CONVIT I8 (REG I64 (HOLE 1 IREG))))
   )
  )

;; == Store Halfword ==
;; sth reg, [address]
(DEFINST ("sth ?1r, [??2A]" "sth ?1r, [??2A]")
  (PARALLEL
   (SET (MEM I16 (HOLE 2)) (CONVIT I16 (REG I64 (HOLE 1 IREG))))
   )
  )

;; == Store Word ==
;; stw reg, [address]
(DEFINST ("stw ?1r, [??2A]" "stw ?1r, [??2A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 2)) (CONVIT I32 (REG I64 (HOLE 1 IREG))))
   )
  )

;; == Store Extended Word ==
;; std reg, [address]
(DEFINST ("stx ?1r, [??2A]" "stx ?1r, [??2A]")
  (PARALLEL
   (SET (MEM I64 (HOLE 2)) (REG I64 (HOLE 1 IREG)))
   )
  )

;; == Store Doubleword ==
;; std reg, [address]
(DEFINST ("std %g0, [??1A]" "std %g0, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 g0)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 g1)))
   )
  )

(DEFINST ("std %g2, [??1A]" "std %g2, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 g2)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 g3)))
   )
  )

(DEFINST ("std %g4, [??1A]" "std %g4, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 g4)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 g5)))
   )
  )

(DEFINST ("std %g6, [??1A]" "std %g6, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 g6)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 g7)))
   )
  )

(DEFINST ("std %o0, [??1A]" "std %o0, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 o0)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 o1)))
   )
  )

(DEFINST ("std %o2, [??1A]" "std %o2, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 o2)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 o3)))
   )
  )

(DEFINST ("std %o4, [??1A]" "std %o4, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 o4)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 o5)))
   )
  )

(DEFINST ("std %o6, [??1A]" "std %o6, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 o6)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 o7)))
   )
  )

(DEFINST ("std %l0, [??1A]" "std %l0, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 l0)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 l1)))
   )
  )

(DEFINST ("std %l2, [??1A]" "std %l2, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 l2)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 l3)))
   )
  )

(DEFINST ("std %l4, [??1A]" "std %l4, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 l4)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 l5)))
   )
  )

(DEFINST ("std %l6, [??1A]" "std %l6, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 l6)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 l7)))
   )
  )

(DEFINST ("std %i0, [??1A]" "std %i0, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 i0)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 i1)))
   )
  )

(DEFINST ("std %i2, [??1A]" "std %i2, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 i2)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 i3)))
   )
  )

(DEFINST ("std %i4, [??1A]" "std %i4, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 i4)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 i5)))
   )
  )

(DEFINST ("std %i6, [??1A]" "std %i6, [??1A]")
  (PARALLEL
   (SET (MEM I32 (HOLE 1))
	(CONVIT I32 (REG I64 i6)))
   (SET (MEM I32 (ADD I64 (HOLE 1) (INTCONST I64 4)))
	(CONVIT I32 (REG I64 i7)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Store Integer into Alternate Space
;;;
;;;	STBA	Store Byte into Alternate space
;;;	STHA	Store Halfword into Alternate space
;;;	STWA	Store Word into Alternate space
;;;	STXA	Store Extended Word into Alternate space
;;;	STDA	Store Doubleword into Alternate space *** Deprecated ***
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Store Byte into Alternate space ==
;; stba reg, [regaddr] imm_asi (synonyms: stuba, stsba)
;; *** Alternate Address Spaceは未サポート ***

;; == Store Halfword into Alternate space ==
;; stha reg, [regaddr] imm_asi (synonyms: stuha, stsha)
;; *** Alternate Address Spaceは未サポート ***

;; == Store Word into Alternate space ==
;; stwa reg, [regaddr] imm_asi (synonyms: sta, stuwa, stswa)
;; *** Alternate Address Spaceは未サポート ***

;; == Store Extended Word into Alternate space ==
;; stxa reg, [regaddr] imm_asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Doubleword into Alternate space ==
;; stda reg, [regaddr] imm_asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Byte into Alternate space ==
;; stba reg, [reg_plus_imm] %asi (synonyms: stuba, stsba)
;; *** Alternate Address Spaceは未サポート ***

;; == Store Halfword into Alternate space ==
;; stha reg, [reg_plus_imm] %asi (synonyms: stuha, stsha)
;; *** Alternate Address Spaceは未サポート ***

;; == Store Word into Alternate space ==
;; stwa reg, [reg_plus_imm] %asi (synonyms: sta, stuwa, stswa)
;; *** Alternate Address Spaceは未サポート ***

;; == Store Extended Word into Alternate space ==
;; stxa reg, [reg_plus_imm] %asi
;; *** Alternate Address Spaceは未サポート ***

;; == Store Doubleword into Alternate space ==
;; stda reg, [reg_plus_imm] %asi
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Subtract
;;;
;;;	SUB	Subtract
;;;	SUBcc	Subtract and modify cc's
;;;	SUBC	Subtract with Carry
;;;	SUBCcc	Subtract with Carry and modify cc's
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Subtracut ==
;; sub reg, reg_or_imm, reg
(DEFINST ("sub ?1r, ??2R, ?3r" "sub ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   )
  )

;; == Subtract and modify cc's ==
;; subcc reg, reg_or_imm, reg
(DEFINST ("subcc ?1r, ??2R, ?3r" "subcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
		(INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1)))
   (SET (REG I1 icc_c)
	(BNOT I1 (CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			 (BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1))))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
		  (INTCONST I1 1)))
   (SET (REG I1 xcc_c)
	(BNOT I1 (CARRY I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
			(INTCONST I1 1))))
   )
  )

;; destinationがg0の場合はフラグのみ設定する
(DEFINST ("subcc ?1r, ??2R, %g0" "subcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1)))
   (SET (REG I1 icc_c)
	(BNOT I1 (CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			 (BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1))))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
		  (INTCONST I1 1)))
   (SET (REG I1 xcc_c)
	(BNOT I1 (CARRY I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
			(INTCONST I1 1))))
   )
  )

;; == Subtract with Carry ==
;; subc reg, reg_or_imm, reg
(DEFINST ("subc ?1r, ??2R, ?3r" "subc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(SUB I64 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	     (CONVZX I64 (REG I1 icc_c))))
   )
  )

;; == Subtract with Carry and modify cc's ==
;; subccc reg, reg_or_imm, reg
(DEFINST ("subccc ?1r, ??2R, ?3r" "subccc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(SUB I64 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	     (CONVZX I64 (REG I1 icc_c))))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
		(CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (BNOT I32 (CONVIT I32 (HOLE 2))) (BNOT I1 (REG I1 icc_c))))
   (SET (REG I1 icc_c)
	(BNOT I1 (CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			 (BNOT I32 (CONVIT I32 (HOLE 2)))
			 (BNOT I1 (REG I1 icc_c)))))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (SUB I64 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
			(CONVZX I64 (REG I1 icc_c)))
		(INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (SUB I64 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
		       (CONVZX I64 (REG I1 icc_c)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
		  (BNOT I1 (REG I1 icc_c))))
   (SET (REG I1 xcc_c)
	(BNOT I1 (CARRY  I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
			 (BNOT I1 (REG I1 icc_c)))))
   )
  )

;; destinationがg0の場合はフラグのみ設定する
(DEFINST ("subccc ?1r, ??2R, %g0" "subccc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
		(CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (CONVIT I32 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
	       (CONVZX I32 (REG I1 icc_c))))
   (SET (REG I1 icc_v)
	(OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		  (BNOT I32 (CONVIT I32 (HOLE 2))) (BNOT I1 (REG I1 icc_c))))
   (SET (REG I1 icc_c)
	(BNOT I1 (CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			 (BNOT I32 (CONVIT I32 (HOLE 2)))
			 (BNOT I1 (REG I1 icc_c)))))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (SUB I64 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
			(CONVZX I64 (REG I1 icc_c)))
		(INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (SUB I64 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
		       (CONVZX I64 (REG I1 icc_c)))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
		  (BNOT I1 (REG I1 icc_c))))
   (SET (REG I1 xcc_c)
	(BNOT I1 (CARRY I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
			(BNOT I1 (REG I1 icc_c)))))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Swap Register with Memory
;;;
;;; *** Deprecated ***
;;;
;;;	SWAP	SWAP register with memory
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == SWAP register with memory ==
;; swap [address], reg
(DEFINST ("swap [??1A], ?2r" "swap [??1A], ?2r")
  (PARALLEL
   (SET (REG I64 (HOLE 2 IREG_D)) (CONVZX I64 (MEM I32 (HOLE 1))))
   (SET (MEM I32 (HOLE 1)) (CONVIT I32 (REG I64 (HOLE 2 IREG_D))))
   )
  )

;; destinationがg0の場合はg0⇒sourceのみ
(DEFINST ("swap [??1A], %g0" "swap [??1A], %g0")
  (PARALLEL
   (SET (MEM I32 (HOLE 1)) (CONVIT I32 (REG I64 g0)))
   )
  )


;;;----------------------------------------------------------------------
;;;
;;; Swap Register with Alternate Space Memory
;;;
;;; *** Deprecated ***
;;;
;;;	SWAPA	SWAP register with Alternate space memory
;;;
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == SWAP register with Alternate space memory ==
;; swapa [regaddr], reg
;; *** Alternate Address Spaceは未サポート ***

;; == SWAP register with Alternate space memory ==
;; swapa [reg_plus_imm]%asi, reg
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Tagged Add
;;;
;;;	TADDcc	Tagged Add and modify cc's
;;;	TADDccTV Tagged Add and modify cc's, or Trap on Overflow *** Deprecated ***
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Tagged Add and modify icc ==
;; taddcc reg, reg_or_imm, reg
(DEFINST ("taddcc ?1r, ??2R, ?3r" "taddcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (ADD I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			(CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (ADD I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(BOR I1
	     (OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (CONVIT I32 (HOLE 2)) (INTCONST I1 0))
	     (TSTNE I1 (BAND I32
			     (BOR I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
				  (CONVIT I32 (HOLE 2)))
			     (INTCONST I32 3))
		    (INTCONST I32 0))))
   (SET (REG I1 icc_c)
	(CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		(CONVIT I32 (HOLE 2)) (INTCONST I1 0)))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   (SET (REG I1 xcc_c)
	(CARRY  I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   )
  )

;; destinationがg0の場合はフラグのみ設定する
(DEFINST ("taddcc ?1r, ??2R, %g0" "taddcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (ADD I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			(CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (ADD I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(BOR I1
	     (OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (CONVIT I32 (HOLE 2)) (INTCONST I1 0))
	     (TSTNE I1 (BAND I32
			     (BOR I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
				  (CONVIT I32 (HOLE 2)))
			     (INTCONST I32 3))
		    (INTCONST I32 0))))
   (SET (REG I1 icc_c)
	(CARRY  I1 (CONVIT I32 (REG I64 (HOLE 1 IREG))) (CONVIT I32 (HOLE 2))
		(INTCONST I1 0)))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (ADD I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   (SET (REG I1 xcc_c)
	(CARRY  I1 (REG I64 (HOLE 1 IREG)) (HOLE 2) (INTCONST I1 0)))
   )
  )

;; == Tagged Add, modify icc and Trap on Overflow ==
;; taddcctv reg, reg_or_imm, reg
;; *** Trapは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Tagged Subtract
;;;
;;;	TSUBcc	Tagged Subtract and modify cc's
;;;	TSUBccTV Tagged Subtract and modify cc's, or Trap on Overflow *** Deprecated ***
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Tagged Subtract and modify icc ==
;; tsubcc reg, reg_or_imm, reg
(DEFINST ("tsubcc ?1r, ??2R, ?3r" "tsubcc ?1r, ??2R, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG_D))
	(SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2)))
   (SET (REG I1 icc_n)
	(TSTLTS I1 (SUB I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			(CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (SUB I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(BOR I1
	     (OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1))
	     (TSTNE I1 (BAND I32
			     (BOR I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
				  (CONVIT I32 (HOLE 2)))
			     (INTCONST I32 3))
		    (INTCONST I32 0))))
   (SET (REG I1 icc_c)
	(BNOT I1 (CARRY I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			(BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1))))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
		  (INTCONST I1 1)))
   (SET (REG I1 xcc_c)
	(BNOT I1 (CARRY I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
			(INTCONST I1 1))))
   )
  )

;; destinationがg0の場合はフラグのみ設定する
(DEFINST ("tsubcc ?1r, ??2R, %g0" "tsubcc ?1r, ??2R, %g0")
  (PARALLEL
   (SET (REG I1 icc_n)
	(TSTLTS I1 (SUB I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			(CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_z)
	(TSTEQ I1 (SUB I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (CONVIT I32 (HOLE 2)))
	       (INTCONST I32 0)))
   (SET (REG I1 icc_v)
	(BOR I1
	     (OVERFLOW I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		       (BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1))
	     (TSTNE I1 (BAND I32
			     (BOR I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
				  (CONVIT I32 (HOLE 2)))
			     (INTCONST I32 3))
		    (INTCONST I32 0))))
   (SET (REG I1 icc_c)
	(BNOT I1 (CARRY I1 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
			(BNOT I32 (CONVIT I32 (HOLE 2))) (INTCONST I1 1))))
   (SET (REG I1 xcc_n)
	(TSTLTS I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_z)
	(TSTEQ I1 (SUB I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
	       (INTCONST I64 0)))
   (SET (REG I1 xcc_v)
	(OVERFLOW I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
		  (INTCONST I1 1)))
   (SET (REG I1 xcc_c)
	(BNOT I1 (CARRY I1 (REG I64 (HOLE 1 IREG)) (BNOT I64 (HOLE 2))
			(INTCONST I1 1))))
   )
  )

;; == Tagged Subtract, modify icc and Trap on Overflow ==
;; tsubcctv reg, reg_or_imm, reg
;; *** Trapは未サポート ***
;;(DEFINST "tsubcctv reg, reg_or_imm, reg")


;;;----------------------------------------------------------------------
;;;
;;; Trap on Integer Condition Codes (Tcc)
;;;
;;;	TA	Trap Always
;;;	TN	Trap Never
;;;	TNE	Trap on Not Equal
;;;	TE	Trap on Equal
;;;	TG	Trap on Greater
;;;	TLE	Trap on Less or Equal
;;;	TGE	Trap on Greater or Equal
;;;	TL	Trap on Less
;;;	TGU	Trap on Greater Unsigned
;;;	TLEU	Trap on Less or Equal Unsigned
;;;	TCC	Trap on Carry Clear (Greater than or Equal, Unsigned)
;;;	TCS	Trap on Carry Set (Less Than, Unsigned)
;;;	TPOS	Trap on Positive or zero
;;;	TNEG	Trap on Negative
;;;	TVC	Trap on Overflow Clear
;;;	TVS	Trap on Overflow Set
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Trap Always ==
;; ta i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap Never ==
;; tn i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Not Equal ==
;; tne i_or_x_cc, software_trap_number (synonym: tnz)
;; *** TRAPは未サポート ***

;; == Trap on Equal ==
;; te i_or_x_cc, software_trap_number (synonym: tz)
;; *** TRAPは未サポート ***

;; == Trap on Greater ==
;; tg i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Less or Equal ==
;; tle i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Greater or Equal ==
;; tge i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Less ==
;; tl i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Greater Unsigned ==
;; tgu i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Less or Equal Unsigned ==
;; tleu i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Carry Clear (Greater than or Equal, Unsigned) ==
;; tcc i_or_x_cc, software_trap_number (synonym: tgeu)
;; *** TRAPは未サポート ***

;; == Trap on Carry Set (Less Than, Unsigned) ==
;; tcs i_or_x_cc, software_trap_number (synonym: tlu)
;; *** TRAPは未サポート ***

;; == Trap on Positive or zero ==
;; tpos i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Negative ==
;; tneg i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Overflow Clear ==
;; tvc i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***

;; == Trap on Overflow Set ==
;; tvs i_or_x_cc, software_trap_number
;; *** TRAPは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Write Privileged Register
;;;
;;;	WRPR	Write Privileged Register
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %tpc
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %tnpc
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %tstate
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %tt
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %tick
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %tba
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %pstate
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %tl
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %pil
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %cwp
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %cansave
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %canrestore
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %cleanwin
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %otherwin
;; *** Privileged Registerは未サポート ***

;; == Write Privileged Register ==
;; wrpr reg, reg_or_imm, %wstate
;; *** Privileged Registerは未サポート ***


;;;----------------------------------------------------------------------
;;;
;;; Write State Register
;;;
;;;	WRY	Write Y register *** Deprecated ***
;;;	WRCCR	Write Condition Codes Register
;;;	WRASI	Write ASI register
;;;	WRASR	Write Ancillary State Register (reserved)
;;;	WRFPRS	Write Floating-Point Registers Status register
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Write Y Register ==
;; wr reg, reg_or_imm, %y
(DEFINST ("wr ?1r, ??2R, %y" "wr ?1r, ??2R, %y")
  (PARALLEL
   (SET (REG I64 Y)
	(CONVZX I64
		(BXOR I32 (CONVIT I32 (REG I64 (HOLE 1 IREG)))
		      (CONVIT I32 (HOLE 2)))))
   )
  )

;; == Write Condition Codes Register ==
;; wr reg, reg_or_imm, %ccr
;; *** %CCRは未サポート ***

;; == Write ASI register ==
;; wr reg, reg_or_imm, %asi
;; *** Alternate Address Spaceは未サポート ***

;; == Write Ancillary State Register (reserved) ==
;; wr reg, reg_or_imm, asr_reg
;; *** %ASRは未サポート ***

;; == Write Floating-Point Registers Status register ==
;; wr reg, reg_or_imm, %fprs
;; *** %FPRSは未サポート ***


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;; VIS Instructions
;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;----------------------------------------------------------------------
;;; Graphics Status Register (GSR)
;;;
;;;	RDASR	Read GSR
;;;	WRASR	Write GSR
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Read GSR ==
;; rd %gsr, reg
(DEFINST ("rd %gsr, ?1r" "rd %gsr, ?1r")
  (PARALLEL
   (SET (REG I64 (HOLE 1 IREG))
	(BOR I64
	     (CONVZX I64 (REG I3 alignaddr_offset))
	     (LSH I64 (CONVZX I64 (REG I4 scale_factor)) (INTCONST I64 3))))
   )
  )

;; == Write GSR ==
;; wr reg, reg_or_imm, %gsr
(DEFINST ("wr ?1r, ??2R, %gsr" "wr ?1r, ??2R, %gsr")
  (PARALLEL
   (SET (REG I3 alignaddr_offset)
	(CONVIT I3 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))))
   (SET (REG I4 scale_factor)
	(CONVIT I4 (RSHU I64 (BXOR I64 (REG I64 (HOLE 1 IREG)) (HOLE 2))
			 (INTCONST I64 3))))
   )
  )


;;;----------------------------------------------------------------------
;;; Partitioned Add/Subtract Instructions
;;;
;;;	FPADD16 	Four 16-bit add
;;;	FPADD16S	Two 16-bit add
;;;	FPADD32		Two 32-bit add
;;;	FPADD32S	One 32-bit add
;;;	FPSUB16		Four 16-bit subtract
;;;	FPSUB16S	Two 16-bit subtract
;;;	FPSUB32		Two 32-bit subtract
;;;	FPSUB32S	One 32-bit subtract
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Four 16-bit add ==
;; fpadd16 freg, freg, freg
(DEFINST ("fpadd16 ?1f, ?2f, ?3f" "fpadd16 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(ADD I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 0)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(ADD I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 1)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 1)))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(ADD I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 2)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 2)))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(ADD I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 3)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 3)))
   )
  )

;; == Two 16-bit add ==
;; fpadd16s freg, freg, freg
(DEFINST ("fpadd16s ??1P, ??2P, ??3P" "fpadd16s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (SUBREG I16 (HOLE 3) 0)
	(ADD I16 (SUBREG I16 (HOLE 1) 0)
	     (SUBREG I16 (HOLE 2) 0)))
   (SET (SUBREG I16 (HOLE 3) 1)
	(ADD I16 (SUBREG I16 (HOLE 1) 1)
	     (SUBREG I16 (HOLE 2) 1)))
   )
  )

;; == Two 32-bit add ==
;;fpadd32 freg, freg, freg
(DEFINST ("fpadd32 ?1f, ?2f, ?3f" "fpadd32 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 0)
	(ADD I32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 0)
	     (SUBREG I32 (REG F64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 1)
	(ADD I32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 1)
	     (SUBREG I32 (REG F64 (HOLE 2 FREG)) 1)))
   )
  )

;; == One 32-bit add ==
;; fpadd32s freg, freg, freg
(DEFINST ("fpadd32s ??1P, ??2P, ??3P" "fpadd32s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(ADD I32 (HOLE 1) (HOLE 2)))
   )
  )

;; == Four 16-bit subtract ==
;;  fpsub16 freg, freg, freg
(DEFINST ("fpsub16 ?1f, ?2f, ?3f" "fpsub16 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(SUB I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 0)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(SUB I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 1)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 1)))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(SUB I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 2)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 2)))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(SUB I16 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 3)
	     (SUBREG I16 (REG F64 (HOLE 2 FREG)) 3)))
   )
  )

;; == Two 16-bit subtract ==
;; fpsub16s freg, freg, freg
(DEFINST ("fpsub16s ??1P, ??2P, ??3P" "fpsub16s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (SUBREG I16 (HOLE 3) 0)
	(SUB I16 (SUBREG I16 (HOLE 1) 0)
	     (SUBREG I16 (HOLE 2) 0)))
   (SET (SUBREG I16 (HOLE 3) 1)
	(SUB I16 (SUBREG I16 (HOLE 1) 1)
	     (SUBREG I16 (HOLE 2) 1)))
   )
  )

;; == Two 32-bit subtract ==
;; fpsub32 freg, freg, freg
(DEFINST ("fpsub32 ?1f, ?2f, ?3f" "fpsub32 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 0)
	(SUB I32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 0)
	     (SUBREG I32 (REG F64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 1)
	(SUB I32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 1)
	     (SUBREG I32 (REG F64 (HOLE 2 FREG)) 1)))
   )
  )

;; == One 32-bit subtract ==
;; fpsub32s freg, freg, freg
(DEFINST ("fpsub32s ??1P, ??2P, ??3P" "fpsub32s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(SUB I32 (HOLE 1) (HOLE 2)))
   )
  )


;;;----------------------------------------------------------------------
;;; Pixel Formatting Instructions
;;;
;;;	FPACK16		Four 16-bit packs
;;;	FPACK32		Two 32-bit packs
;;;	FPACKFIX	Four 16-bit packs
;;;	FEXPAND		Four 16-bit expands
;;;	FPMERGE		Two 32-bit merges
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Four 16-bit packs ==
;; fpack16 freg, freg
(DEFINST ("fpack16 ?1f, ??2F" "fpack16 ?1f, ??2F")
  (PARALLEL
   (SET (SUBREG I8 (HOLE 2) 0)
	(CONVIT I8
		(RSHU I32
		      (LSH I32 (CONVZX I32
				       (SUBREG I16 (REG F64 (HOLE 1 FREG)) 0))
			   (REG I4 scale_factor))
		      (INTCONST I32 7))))
   (SET (SUBREG I8 (HOLE 2) 1)
	(CONVIT I8
		(RSHU I32
		      (LSH I32 (CONVZX I32
				       (SUBREG I16 (REG F64 (HOLE 1 FREG)) 1))
			   (REG I4 scale_factor))
		      (INTCONST I32 7))))
   (SET (SUBREG I8 (HOLE 2) 2)
	(CONVIT I8
		(RSHU I32
		      (LSH I32 (CONVZX I32
				       (SUBREG I16 (REG F64 (HOLE 1 FREG)) 2))
			   (REG I4 scale_factor))
		      (INTCONST I32 7))))
   (SET (SUBREG I8 (HOLE 2) 3)
	(CONVIT I8
		(RSHU I32
		      (LSH I32 (CONVZX I32
				       (SUBREG I16 (REG F64 (HOLE 1 FREG)) 3))
			   (REG I4 scale_factor))
		      (INTCONST I32 7))))
   )
  )

;; == Two 32-bit packs ==
;; fpack32 freg, freg, freg
(DEFINST ("fpack32 ?1f, ?2f, ?3f" "fpack32 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 0)
	(BOR I32
	     (LSH I32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 0) (INTCONST I32 8))
	     (CONVZX I32
	      (CONVIT I8
	       (RSHU I32
		(CONVIT I32
		 (LSH I64 (CONVZX I64 (SUBREG I32 (REG F64 (HOLE 2 FREG)) 0))
		      (REG I4 scale_factor)))
		(INTCONST I32 23))))))
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 1)
	(BOR I32
	     (LSH I32 (SUBREG I32 (REG F64 (HOLE 1 FREG)) 1) (INTCONST I32 8))
	     (CONVZX I32
	      (CONVIT I8
	       (RSHU I32
		(CONVIT I32
		 (LSH I64 (CONVZX I64 (SUBREG I32 (REG F64 (HOLE 2 FREG)) 1))
		      (REG I4 scale_factor)))
		(INTCONST I32 23))))))
   )
  )

;; == Two 32-bit fixed packs ==
;; fpackfix freg, freg
(DEFINST ("fpackfix ?1f, ??2F" "fpackfix ?1f, ??2F")
  (PARALLEL
   (SET (SUBREG I16 (HOLE 2) 0)
	(CONVIT I16
	 (RSHU I32
	  (LSH I32 (CONVZX I32 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 0))
	       (REG I4 scale_factor))
	  (INTCONST I32 16))))
   (SET (SUBREG I16 (HOLE 2) 1)
	(CONVIT I16
	 (RSHU I32
	  (LSH I32 (CONVZX I32 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 1))
	       (REG I4 scale_factor))
	  (INTCONST I32 16))))
   )
  )

;; == Four 16-bit expands ==
;; fexpand freg, freg
(DEFINST ("fexpand ??1P, ?2f" "fexpand ??1P, ?2f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 2 FREG)) 0)
	(LSH I16
	     (CONVZX I16 (SUBREG I8 (HOLE 1) 0))
	     (INTCONST I16 4)))
   (SET (SUBREG I16 (REG F64 (HOLE 2 FREG)) 1)
	(LSH I16
	     (CONVZX I16 (SUBREG I8 (HOLE 1) 1))
	     (INTCONST I16 4)))
   (SET (SUBREG I16 (REG F64 (HOLE 2 FREG)) 2)
	(LSH I16
	     (CONVZX I16 (SUBREG I8 (HOLE 1) 2))
	     (INTCONST I16 4)))
   (SET (SUBREG I16 (REG F64 (HOLE 2 FREG)) 3)
	(LSH I16
	     (CONVZX I16 (SUBREG I8 (HOLE 1) 3))
	     (INTCONST I16 4)))
   )
  )

;; == Two 32-bit merges ==
;; fpmerge freg, freg, freg
(DEFINST ("fpmerge ??1P, ??2P, ?3f" "fpmerge ??1P, ??2P, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(BOR I16
	     (LSH I16
		  (CONVZX I16 (SUBREG I8 (HOLE 1) 0))
		  (INTCONST I16 8))
	     (CONVZX I16 (SUBREG I8 (HOLE 2) 0))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(BOR I16
	     (LSH I16
		  (CONVZX I16 (SUBREG I8 (HOLE 1) 1))
		  (INTCONST I16 8))
	     (CONVZX I16 (SUBREG I8 (HOLE 2) 1))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(BOR I16
	     (LSH I16
		  (CONVZX I16 (SUBREG I8 (HOLE 1) 2))
		  (INTCONST I16 8))
	     (CONVZX I16 (SUBREG I8 (HOLE 2) 2))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(BOR I16
	     (LSH I16
		  (CONVZX I16 (SUBREG I8 (HOLE 1) 3))
		  (INTCONST I16 8))
	     (CONVZX I16 (SUBREG I8 (HOLE 2) 3))))
   )
  )

;;;----------------------------------------------------------------------
;;; Partitioned Multiply Instructions
;;;
;;;	FMUL8x16	8- × 16-bit partitioned product
;;;	FMUL8x16AU	8- × 16-bit upper a partitioned product
;;;	FMUL8x16AL	8- × 16-bit lower a partitioned product
;;;	FMUL8SUx16	upper 8- × 16-bit partitioned product
;;;	FMUL8ULx16	lower unsigned 8- × 16-bit partitioned product
;;;	FMULD8SUx16	upper 8- × 16-bit partitioned product
;;;	FMULD8ULx16	lower unsigned 8- × 16-bit partitioned product
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == 8- × 16-bit partitioned product ==
;; fmul8x16 freg, freg, freg
(DEFINST ("fmul8x16 ??1P, ?2f, ?3f" "fmul8x16 ??1P, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 0))
			   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 0)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 1))
			   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 1)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 2))
			   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 2)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 3))
			   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 3)))
		      (INTCONST I32 8))))
   )
  )

;; == 8- × 16-bit upper a partitioned product ==
;; fmul8x16au freg, freg, freg
(DEFINST ("fmul8x16au ??1P, ??2P, ?3f" "fmul8x16au ??1P, ??2P, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 0))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 1)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 1))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 1)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 2))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 1)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 3))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 1)))
		      (INTCONST I32 8))))
   )
  )

;; == 8- × 16-bit lower a partitioned product ==
;; fmul8x16al freg, freg, freg
(DEFINST ("fmul8x16al ??1P, ??2P, ?3f" "fmul8x16al ??1P, ??2P, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 0))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 0)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 1))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 0)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 2))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 0)))
		      (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(CONVIT I16
		(RSHU I32
		      (MUL I32 (CONVZX I32 (SUBREG I8 (HOLE 1) 3))
			   (CONVSX I32 (SUBREG I16 (HOLE 2) 0)))
		      (INTCONST I32 8))))
   )
  )

;; == upper 8- × 16-bit partitioned product ==
;; fmul8sux16 freg, freg, freg
(DEFINST ("fmul8sux16 ?1f, ?2f, ?3f" "fmul8sux16 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (RSHS I32 (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 0))
		 (INTCONST I32 8))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 0)))
	  (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (RSHS I32 (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 1))
		 (INTCONST I32 8))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 1)))
	  (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (RSHS I32 (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 2))
		 (INTCONST I32 8))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 2)))
	  (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (RSHS I32 (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 3))
		 (INTCONST I32 8))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 3)))
	  (INTCONST I32 8))))
   )
  )

;; == lower unsigned 8- × 16-bit partitioned product ==
;; fmul8ulx16 freg, freg, freg
(DEFINST ("fmul8ulx16 ?1f, ?2f, ?3f" "fmul8ulx16 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 0)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (CONVZX I32 (CONVIT I8 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 0)))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 0)))
	  (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 1)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (CONVZX I32 (CONVIT I8 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 1)))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 1)))
	  (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 2)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (CONVZX I32 (CONVIT I8 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 2)))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 2)))
	  (INTCONST I32 8))))
   (SET (SUBREG I16 (REG F64 (HOLE 3 FREG)) 3)
	(CONVIT I16
	 (RSHU I32
	  (MUL I32
	   (CONVZX I32 (CONVIT I8 (SUBREG I16 (REG F64 (HOLE 1 FREG)) 3)))
	   (CONVSX I32 (SUBREG I16 (REG F64 (HOLE 2 FREG)) 3)))
	  (INTCONST I32 8))))
   )
  )

;; == upper 8- × 16-bit partitioned product ==
;; fmuld8sux16 freg, freg, freg
(DEFINST ("fmuld8sux16 ??1P, ??2P, ?3f" "fmuld8sux16 ??1P, ??2P, ?3f")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 0)
	(RSHU I32
	 (MUL I32 (RSHS I32 (CONVSX I32 (SUBREG I16 (HOLE 1) 0))
			(INTCONST I32 8))
	      (CONVSX I32 (SUBREG I16 (HOLE 2) 0)))
	 (INTCONST I32 8)))
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 1)
	(RSHU I32
	 (MUL I32 (RSHS I32 (CONVSX I32 (SUBREG I16 (HOLE 1) 1))
			(INTCONST I32 8))
	      (CONVSX I32 (SUBREG I16 (HOLE 2) 1)))
	 (INTCONST I32 8)))
   )
  )
  

;; == lower unsigned 8- × 16-bit partitioned product ==
;; fmuld8ulx16 freg, freg, freg
(DEFINST ("fmuld8ulx16 ??1P, ??2P, ?3f" "fmuld8ulx16 ??1P, ??2P, ?3f")
  (PARALLEL
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 0)
	(MUL I32 (CONVZX I32 (CONVIT I8 (SUBREG I16 (HOLE 1) 0)))
	     (CONVSX I32 (SUBREG I16 (HOLE 2) 0))))
   (SET (SUBREG I32 (REG F64 (HOLE 3 FREG)) 1)
	(MUL I32 (CONVZX I32 (CONVIT I8 (SUBREG I16 (HOLE 1) 1)))
	     (CONVSX I32 (SUBREG I16 (HOLE 2) 1))))
   )
  )

;;;----------------------------------------------------------------------
;;; Alignment Instructions
;;;
;;;	ALIGNADDRESS		Calculate address for misaligned data access
;;;	ALIGNADDRESS_LITTLE	Calculate address for misaligned data access,
;;;				little-endian
;;;	FALIGNDATA		Perform data alignment for misaligned data
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Calculate address for misaligned data access ==
;; alignaddr reg, reg, reg
(DEFINST ("alignaddr ?1r, ?2r, ?3r" "alignaddr ?1r, ?2r, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(BAND I64
	      (ADD I64 (REG I64 (HOLE 1 IREG)) (REG I64 (HOLE 2 IREG)))
	      (INTCONST I64 #xfffffffffffffff8)))
   (SET (REG I3 alignaddr_offset)
	(CONVIT I3 (ADD I64 (REG I64 (HOLE 1 IREG)) (REG I64 (HOLE 2 IREG)))))
   )
  )

;; == Calculate address for misaligned data access, little-endian
;; alignaddrl reg, reg, reg
(DEFINST ("alignaddrl ?1r, ?2r, ?3r" "alignaddrl ?1r, ?2r, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(BAND I64
	      (ADD I64 (REG I64 (HOLE 1 IREG)) (REG I64 (HOLE 2 IREG)))
	      (INTCONST I64 #xfffffffffffffff8)))
   (SET (REG I3 alignaddr_offset)
	(NEG I3
	 (CONVIT I3 (ADD I64 (REG I64 (HOLE 1 IREG))
			 (REG I64 (HOLE 2 IREG))))))
   )
  )

;; == Perform data alignment for misaligned data ==
;; faligndata freg
(DEFINST ("aligndata ?1f, ?2f, ?3f" "aligndata ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(CONVIT I64
	 (RSHU I128
	  (BOR I128
	   (LSH I128 (CONVZX I128 (REG I64 (HOLE 1 FREG))) (INTCONST I32 64))
	   (CONVZX I128 (REG I64 (HOLE 2 FREG))))
	  (REG I3 alignaddr_offset))))
   )
  )


;;;----------------------------------------------------------------------
;;; Logical Operate Instructions
;;;
;;;	FZERO		Zero fill
;;;	FZEROS		Zero fill, single precision
;;;	FONE		One fill
;;;	FONES		One fill, single precision
;;;	FSRC1		Copy src1
;;;	FSRC1S		Copy src1, single precision
;;;	FSRC2		Copy src2
;;;	FSRC2S		Copy src2, single precision
;;;	FNOT1		Negate (1s complement) src1
;;;	FNOT1S		Negate (1s complement) src1, single precision
;;;	FNOT2		Negate (1s complement) src2
;;;	FNOT2S		Negate (1s complement) src2, single precision
;;;	FOR		Logical OR
;;;	FORS		Logical OR, single precision
;;;	FNOR		Logical NOR
;;;	FNORS		Logical NOR, single precision
;;;	FAND		Logical AND
;;;	FANDS		Logical AND, single precision
;;;	FNAND		Logical NAND
;;;	FNANDS		Logical NAND, single precision
;;;	FXOR		Logical XOR
;;;	FXORS		Logical XOR, single precision
;;;	FXNOR		Logical XNOR
;;;	FXNORS		Logical XNOR, single precision
;;;	FORNOT1		Negated src1 OR src2
;;;	FORNOT1S	Negated src1 OR src2, single precision
;;;	FORNOT2		Src1 OR negated src2
;;;	FORNOT2S	Src1 OR negated src2, single precision
;;;	FANDNOT1	Negated src1 AND src2
;;;	FANDNOT1S	Negated src1 AND src2, single precision
;;;	FANDNOT2	Src1 AND negated src2
;;;	FANDNOT2S	Src1 AND negated src2, single precision
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Zero fill ==
;; fzero freg
(DEFINST ("fzero ?1f" "fzero ?1f")
  (PARALLEL
   (SET (REG I64 (HOLE 1 FREG))
	(INTCONST I64 0))
   )
  )

;; ==  Zero fill, single precision ==
;; fzeros freg
(DEFINST ("fzeros ??1P" "fzeros ??1P")
  (PARALLEL
   (SET (HOLE 1)
	(INTCONST I32 0))
   )
  )

;; == One fill ==
;; fone freg
(DEFINST ("fone ?1f" "fone ?1f")
  (PARALLEL
   (SET (REG I64 (HOLE 1 FREG))
	(INTCONST I64 #xffffffffffffffff))
   )
  )

;; == One fill, single precision ==
;; fones freg
(DEFINST ("fones ??1P" "fones ??1P")
  (PARALLEL
   (SET (HOLE 1)
	(INTCONST I32 #xffffffff))
   )
  )

;; == Copy src1 ==
;; fsrc1 freg, freg
(DEFINST ("fsrc1 ?1f, ?2f" "fsrc1 ?1f, ?2f")
  (PARALLEL
   (SET (REG I64 (HOLE 2 FREG))
	(REG I64 (HOLE 1 FREG)))
   )
  )

;; == Copy src1, single precision ==
;; fsrc1s freg, freg
(DEFINST ("fsrc1s ??1P, ??2P" "fsrc1s ??1P, ??2P")
  (PARALLEL
   (SET (HOLE 2) (HOLE 1))
   )
  )

;; == Copy src2 ==
;; fsrc2 freg, freg
;;(DEFINST ("fsrc2 ?1f, ?2f" "fsrc2 ?1f, ?2f")
;;  (PARALLEL
;;   (SET (REG I64 (HOLE 2 FREG))
;;	(REG I64 (HOLE 1 FREG)))
;;   )
;;  )

;; == Copy src2, single precision ==
;; fsrc2s freg, freg
;;(DEFINST ("fsrc2s ??1P, ??2P" "fsrc2s ??1P, ??2P")
;;  (PARALLEL
;;   (SET (REG I32 (HOLE 2))
;;	(REG I32 (HOLE 1)))
;;   )
;;  )

;; == Negate (1s complement) src1 ==
;; fnot1 freg, freg
(DEFINST ("fnot1 ?1f, ?2f" "fnot1 ?1f, ?2f")
  (PARALLEL
   (SET (REG I64 (HOLE 2 FREG))
	(BNOT I64 (REG I64 (HOLE 1 FREG))))
   )
  )

;; == Negate (1s complement) src1, single precision ==
;; fnot1s freg, freg
(DEFINST ("fnot1s ??1P, ??2P" "fnot1s ??1P, ??2P")
  (PARALLEL
   (SET (HOLE 2) (BNOT I32 (HOLE 1)))
   )
  )

;; == Negate (1s complement) src2 ==
;; fnot2 freg, freg
;;(DEFINST ("fnot2 ?1f, ?2f" "fnot2 ?1f, ?2f")
;;  (PARALLEL
;;   (SET (REG I64 (HOLE 2 FREG))
;;	(BNOT I64 (REG I64 (HOLE 1 FREG))))
;;   )
;;  )

;; == Negate (1s complement) src2, single precision ==
;; fnot2s freg, freg
;;(DEFINST ("fnot2s ??1P, ??2P" "fnot2s ??1P, ??2P")
;;  (PARALLEL
;;   (SET (REG I32 (HOLE 2))
;;	(BNOT I32 (REG I32 (HOLE 1))))
;;   )
;;  )

;; == Logical OR ==
;; for freg, freg, freg
(DEFINST ("for ?1f, ?2f, ?3f" "for ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BOR I64
	     (REG I64 (HOLE 1 FREG))
	     (REG I64 (HOLE 2 FREG))))
   )
  )

;; == Logical OR, single precision ==
;; fors freg, freg, freg
(DEFINST ("fors ??1P, ??2P, ??3P" "fors ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3) (BOR I32 (HOLE 1) (HOLE 2)))
   )
  )

;; == Logical NOR ==
;; fnor freg, freg, freg
(DEFINST ("fnor ?1f, ?2f, ?3f" "fnor ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BNOT I64
	      (BOR I64
		   (REG I64 (HOLE 1 FREG))
		   (REG I64 (HOLE 2 FREG)))))
   )
  )

;; == Logical NOR, single precision ==
;; fnors freg, freg, freg
(DEFINST ("fnors ??1P, ??2P, ??3P" "fnors ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3) (BNOT I32 (BOR I32 (HOLE 1) (HOLE 2))))
   )
  )

;; == Logical AND ==
;; fand freg, freg, freg
(DEFINST ("fand ?1f, ?2f, ?3f" "fand ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BAND I64
	     (REG I64 (HOLE 1 FREG))
	     (REG I64 (HOLE 2 FREG))))
   )
  )

;; == Logical AND, single precision ==
;; fands freg, freg, freg
(DEFINST ("fands ??1P, ??2P, ??3P" "fands ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3) (BAND I32 (HOLE 1) (HOLE 2)))
   )
  )

;; == Logical NAND ==
;; fnand freg, freg, freg
(DEFINST ("fnand ?1f, ?2f, ?3f" "fnand ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BNOT I64
	      (BAND I64
		    (REG I64 (HOLE 1 FREG))
		    (REG I64 (HOLE 2 FREG)))))
   )
  )


;; == Logical NAND, single precision ==
;; fnands freg, freg, freg
(DEFINST ("fnands ??1P, ??2P, ??3P" "fnands ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(BNOT I32 (BAND I32 (HOLE 1) (HOLE 2))))
   )
  )

;; == Logical XOR ==
;; fxor freg, freg, freg
(DEFINST ("fxor ?1f, ?2f, ?3f" "fxor ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BXOR I64
	     (REG I64 (HOLE 1 FREG))
	     (REG I64 (HOLE 2 FREG))))
   )
  )

;; == Logical XOR, single precision ==
;; fxors freg, freg, freg
(DEFINST ("fxors ??1P, ??2P, ??3P" "fxors ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(BXOR I32 (HOLE 1) (HOLE 2)))
   )
  )

;; == Logical XNOR ==
;; fxnor freg, freg, freg
(DEFINST ("fxnor ?1f, ?2f, ?3f" "fxnor ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BNOT I64
	      (BXOR I64
		    (REG I64 (HOLE 1 FREG))
		    (REG I64 (HOLE 2 FREG)))))
   )
  )

;; == Logical XNOR, single precision ==
;; fxnors freg, freg, freg
(DEFINST ("fxors ??1P, ??2P, ??3P" "fxors ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(BNOT I32 (BXOR I32 (HOLE 1) (HOLE 2))))
   )
  )

;; == Negated src1 OR src2 ==
;; fornot1 freg, freg, freg
(DEFINST ("fornot1 ?1f, ?2f, ?3f" "fornot1 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BOR I64
	      (BNOT I64 (REG I64 (HOLE 1 FREG)))
	      (REG I64 (HOLE 2 FREG))))
   )
  )

;; == Negated src1 OR src2, single precision ==
;; fornot1s freg, freg, freg
(DEFINST ("fornot1s ??1P, ??2P, ??3P" "fornot1s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(BOR I32 (BNOT I32 (HOLE 1)) (HOLE 2)))
   )
  )

;; == Src1 OR negated src2 ==
;; fornot2 freg, freg, freg
(DEFINST ("fornot2 ?1f, ?2f, ?3f" "fornot2 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BOR I64
	     (REG I64 (HOLE 1 FREG))
	     (BNOT I64 (REG I64 (HOLE 2 FREG)))))
   )
  )

;; == Src1 OR negated src2, single precision ==
;; fornot2s freg, freg, freg
(DEFINST ("fornot2s ??1P, ??2P, ??3P" "fornot2s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(BOR I32 (HOLE 1) (BNOT I32 (HOLE 2))))
   )
  )

;; == Negated src1 AND src2 ==
;; fandnot1 freg, freg, freg
(DEFINST ("fandnot1 ?1f, ?2f, ?3f" "fandnot1 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BAND I64
	      (BNOT I64 (REG I64 (HOLE 1 FREG)))
	      (REG I64 (HOLE 2 FREG))))
   )
  )

;; == Negated src1 AND src2, single precision ==
;; fandnot1s freg, freg, freg
(DEFINST ("fandnot1s ??1P, ??2P, ??3P" "fandnot1s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(BAND I32 (BNOT I32 (HOLE 1)) (HOLE 2)))
   )
  )

;; == Src1 AND negated src2 ==
;; fandnot2 freg, freg, freg
(DEFINST ("fandnot2 ?1f, ?2f, ?3f" "fandnot2 ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (REG I64 (HOLE 3 FREG))
	(BAND I64
	     (REG I64 (HOLE 1 FREG))
	     (BNOT I64 (REG I64 (HOLE 2 FREG)))))
   )
  )

;; == Src1 AND negated src2, single precision ==
;; fandnot2 freg, freg, freg
(DEFINST ("fandnot2s ??1P, ??2P, ??3P" "fandnot2s ??1P, ??2P, ??3P")
  (PARALLEL
   (SET (HOLE 3)
	(BAND I32 (HOLE 1) (BNOT I32 (HOLE 2))))
   )
  )


;;;----------------------------------------------------------------------
;;; Pixel Compare Instructions
;;;
;;;	FCMPGT16	Four 16-bit compare; set rd if src1 ＞ src2
;;;	FCMPGT32	Two 32-bit compare; set rd if src1 ＞ src2
;;;	FCMPLE16	Four 16-bit compare; set rd if src1 ≦ src2
;;;	FCMPLE32	Two 32-bit compare; set rd if src1 ≦ src2
;;;	FCMPNE16	Four 16-bit compare; set rd if src1 ≠ src2
;;;	FCMPNE32	Two 32-bit compare; set rd if src1 ≠ src2
;;;	FCMPEQ16	Four 16-bit compare; set rd if src1 ＝ src2
;;;	FCMPEQ32	Two 32-bit compare; set rd if src1 ＝ src2
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Four 16-bit compare; set rd if src1 ＞ src2 ==
;; fcmpgt16 freg, freg, reg
(DEFINST ("fcmpgt16 ?1f, ?2f, ?3r" "fcmpgt16 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTGTS I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTGTS I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 1)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 2)
	(TSTGTS I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 2)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 2)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 3)
	(TSTGTS I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 3)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 3)))
   )
  )

;; == Two 32-bit compare; set rd if src1 ＞ src2 ==
;; fcmpgt32 freg, freg, reg
(DEFINST ("fcmpgt32 ?1f, ?2f, ?3r" "fcmpgt32 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTGTS I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTGTS I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 1)))
   )
  )

;; == Four 16-bit compare; set rd if src1 ≦ src2 ==
;; fcmple16 freg, freg, reg
(DEFINST ("fcmple16 ?1f, ?2f, ?3r" "fcmple16 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTLES I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTLES I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 1)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 2)
	(TSTLES I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 2)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 2)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 3)
	(TSTLES I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 3)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 3)))
   )
  )

;; == Two 32-bit compare; set rd if src1 ≦ src2 ==
;; fcmple32 freg, freg, reg
(DEFINST ("fcmple32 ?1f, ?2f, ?3r" "fcmple32 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTLES I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTLES I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 1)))
   )
  )

;; == Four 16-bit compare; set rd if src1 ≠ src2 ==
;; fcmpne16 freg, freg, reg
(DEFINST ("fcmpne16 ?1f, ?2f, ?3r" "fcmpne16 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTNE I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTNE I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 1)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 2)
	(TSTNE I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 2)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 2)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 3)
	(TSTNE I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 3)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 3)))
   )
  )

;; == Two 32-bit compare; set rd if src1 ≠ src2 ==
;; fcmpne32 freg, freg, reg
(DEFINST ("fcmpne32 ?1f, ?2f, ?3r" "fcmpne32 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTNE I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTNE I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 1)))
   )
  )

;; == Four 16-bit compare; set rd if src1 ＝ src2 ==
;; fcmpeq16 freg, freg, reg
(DEFINST ("fcmpeq16 ?1f, ?2f, ?3r" "fcmpeq16 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTEQ I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTEQ I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 1)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 2)
	(TSTEQ I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 2)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 2)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 3)
	(TSTEQ I1 (SUBREG I16 (REG I64 (HOLE 1 FREG)) 3)
		(SUBREG I16 (REG I64 (HOLE 2 FREG)) 3)))
   )
  )

;; == Two 32-bit compare; set rd if src1 ＝ src2 ==
;; fcmpeq32 freg, freg, reg
(DEFINST ("fcmpeq32 ?1f, ?2f, ?3r" "fcmpeq32 ?1f, ?2f, ?3r")
  (PARALLEL
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 0)
	(TSTEQ I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 0)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 0)))
   (SET (SUBREG I1 (REG I64 (HOLE 3 IREG)) 1)
	(TSTEQ I1 (SUBREG I32 (REG I64 (HOLE 1 FREG)) 1)
		(SUBREG I32 (REG I64 (HOLE 2 FREG)) 1)))
   )
  )


;;;----------------------------------------------------------------------
;;; Edge Handling Instructions
;;;
;;;	EDGE8		Eight 8-bit edge boundary processing
;;;	EDGE8L		Eight 8-bit edge boundary processing, little-endian
;;;	EDGE16		Four 16-bit edge boundary processing
;;;	EDGE16L		Four 16-bit edge boundary processing, little-endian
;;;	EDGE32		Four 32-bit edge boundary processing
;;;	EDGE32L		Two 32-bit edge boundary processing, little-endian
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Eight 8-bit edge boundary processing ==
;; edge8 reg, reg, reg
(DEFINST ("edge8 ?1r, ?2r, ?3r" "edge8 ?1r, ?2r, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64
		    (TSTEQ I1
		     (BAND I64 (REG I64 (HOLE 1 IREG))
			   (INTCONST I64 #xfffffff8))
		     (BAND I64 (REG I64 (HOLE 2 IREG))
			   (INTCONST I64 #xfffffff8)))
		    (BAND I64
			  ;; Left Edge
			  (CONVZX I64
			   (SUB I32
			    (LSH I32 (INTCONST I32 1)
				 (ADD I64 (BAND I64 (REG I64 (HOLE 1 IREG))
						(INTCONST I64 7))
				      (INTCONST I64 1)))
			    (INTCONST I32 1)))
			  ;; Right Edge
			  (BNOT I64
			   (CONVZX I64
			    (SUB I32 (LSH I32 (INTCONST I32 1)
			     (BAND I64 (REG I64 (HOLE 2 IREG))
				   (INTCONST I64 7)))
				 (INTCONST I32 1)))))
		    ;; Left Edge
		    (CONVZX I64
		     (SUB I32 (LSH I32 (INTCONST I32 1)
				   (ADD I64 (BAND I64 (REG I64 (HOLE 1 IREG))
						  (INTCONST I64 7))
					(INTCONST I64 1)))
			  (INTCONST I32 1)))))
   )
  )

;; == Eight 8-bit edge boundary processing, little-endian ==
;; edge8l reg, reg, reg
;; *** little-endianは未サポート ***

;; == Four 16-bit edge boundary processing ==
;; edge16 reg, reg, reg
(DEFINST ("edge16 ?1r, ?2r, ?3r" "edge16 ?1r, ?2r, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64
		    (TSTEQ I1
		     (BAND I64 (REG I64 (HOLE 1 IREG))
			   (INTCONST I64 #xfffffff8))
		     (BAND I64 (REG I64 (HOLE 2 IREG))
			   (INTCONST I64 #xfffffff8)))
		    (BAND I64
			  ;; Left Edge
			  (CONVZX I64
			   (SUB I32
			    (LSH I32 (INTCONST I32 1)
			     (RSHU I64
			      (ADD I64 (BAND I64 (REG I64 (HOLE 1 IREG))
					     (INTCONST I64 7))
				   (INTCONST I64 1)) (INTCONST I64 1)))
			    (INTCONST I32 1)))
			  ;; Right Edge
			  (BNOT I64
			   (CONVZX I64
			    (SUB I32 (LSH I32 (INTCONST I32 1)
			     (RSHU I64 (BAND I64 (REG I64 (HOLE 2 IREG))
					     (INTCONST I64 7))
				   (INTCONST I64 1)))
				 (INTCONST I32 1)))))
		    ;; Left Edge
		    (CONVZX I64
		     (SUB I32
		      (LSH I32 (INTCONST I32 1)
		       (RSHU I64 (ADD I64 (BAND I64 (REG I64 (HOLE 1 IREG))
						(INTCONST I64 7))
				      (INTCONST I64 1)) (INTCONST I64 1)))
		      (INTCONST I32 1)))))
   )
  )

;; == Four 16-bit edge boundary processing, little-endian ==
;; edge16l reg, reg, reg
;; *** little-endianは未サポート ***

;; == Four 32-bit edge boundary processing ==
;; edge32 reg, reg, reg
(DEFINST ("edge32 ?1r, ?2r, ?3r" "edge32 ?1r, ?2r, ?3r")
  (PARALLEL
   (SET (REG I64 (HOLE 3 IREG))
	(IFTHENELSE I64
		    (TSTEQ I1
		     (BAND I64 (REG I64 (HOLE 1 IREG))
			   (INTCONST I64 #xfffffff8))
		     (BAND I64 (REG I64 (HOLE 2 IREG))
			   (INTCONST I64 #xfffffff8)))
		    (BAND I64
			  ;; Left Edge
			  (CONVZX I64
			   (SUB I32
			    (LSH I32 (INTCONST I32 1)
			     (RSHU I64
			      (ADD I64 (BAND I64 (REG I64 (HOLE 1 IREG))
					     (INTCONST I64 7))
				   (INTCONST I64 1)) (INTCONST I64 2)))
			    (INTCONST I32 1)))
			  ;; Right Edge
			  (BNOT I64
			   (CONVZX I64
			    (SUB I32
			     (LSH I32 (INTCONST I32 1)
			      (RSHU I64 (BAND I64 (REG I64 (HOLE 2 IREG))
					      (INTCONST I64 7))
				    (INTCONST I64 2)))
			     (INTCONST I32 1)))))
		    ;; Left Edge
		    (CONVZX I64
		     (SUB I32
		      (LSH I32 (INTCONST I32 1)
			   (RSHU I64
			    (ADD I64 (BAND I64 (REG I64 (HOLE 1 IREG))
					   (INTCONST I64 7))
				 (INTCONST I64 1)) (INTCONST I64 2)))
		      (INTCONST I32 1)))))
   )
  )

;; == Two 32-bit edge boundary processing, little-endian ==
;; edge32l reg, reg, reg
;; *** little-endianは未サポート ***


;;;----------------------------------------------------------------------
;;; Pixel Component Distance (PDIST)
;;;
;;;	PDIST		distance between 8 8-bit components
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == distance between 8 8-bit components ==
;; pdist freg, freg, freg
(DEFINST ("pdist ?1f, ?2f, ?3f" "pdist ?1f, ?2f, ?3f")
  (PARALLEL
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 0)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 0)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 0))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 0)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 0)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 0)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 0))))
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 1)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 1)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 1))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 1)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 1)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 1)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 1))))
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 2)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 2)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 2))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 2)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 2)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 2)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 2))))
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 3)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 3)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 3))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 3)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 3)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 3)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 3))))
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 4)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 4)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 4))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 4)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 4)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 4)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 4))))
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 5)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 5)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 5))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 5)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 5)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 5)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 5))))
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 6)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 6)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 6))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 6)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 6)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 6)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 6))))
   (SET (SUBREG I8 (REG F64 (HOLE 3 FREG)) 7)
	(IFTHENELSE I8
		    (TSTLES I1 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 7)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 7))
			    (INTCONST I8 0))
		    (NEG I8 (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 7)
				    (SUBREG I8 (REG F64 (HOLE 2 FREG)) 7)))
		    (SUB I8 (SUBREG I8 (REG F64 (HOLE 1 FREG)) 7)
			 (SUBREG I8 (REG F64 (HOLE 2 FREG)) 7))))
   )
  )

;;;----------------------------------------------------------------------
;;; Three-Dimensional Array Addressing Instructions
;;;
;;;	ARRAY8		Convert 8-bit 3-D address to blocked byte address
;;;	ARRAY16		Convert 16-bit 3-D address to blocked byte address
;;;	ARRAY32		Convert 32-bit 3-D address to blocked byte address
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Convert 8-bit 3-D address to blocked byte address ==
;; array8 reg, reg, reg
;;(DEFINST ("array8 ?1r, ?2r, ?3r" "array8 ?1r, ?2r, ?3r")
;;  (PARALLEL
;;   ;; int value of X
;;   (BAND I64
;;	 (RSHU I64 (REG I64 (HOLE 1 IREG)) (INTCONST I32 11))
;;	 (INTCONST I64 #x3ff))
;;   ;; int value of Y
;;   (BAND I64
;;	 (RSHU I64 (REG I64 (HOLE 1 IREG)) (INTCONST I32 33))
;;	 (INTCONST I64 #x3ff))
;;   ;; int value of Z
;;   (BAND I64
;;	 (RSHU I64 (REG I64 (HOLE 1 IREG)) (INTCONST I32 55))
;;	 (INTCONST I64 #x1ff))
;;   )
;;  )

;; == Convert 16-bit 3-D address to blocked byte address ==
;; array16 reg, reg, reg

;; == Convert 32-bit 3-D address to blocked byte address ==
;; array32 reg, reg, reg


;;;----------------------------------------------------------------------
;;; Partial Store Instructions
;;;
;;;	STDFA(ASI_PST8_P, 0xC0)		Eight 8-bit conditional stores to
;;;					primary address space
;;;	STDFA(ASI_PST8_S, 0xC1)		Eight 8-bit conditional stores to
;;;					secondary address space
;;;	STDFA(ASI_PST8_PL, 0xC8)	Eight 8-bit conditional stores to
;;;					primary address space, little-endian
;;;	STDFA(ASI_PST8_SL, 0xC9)	Eight 8-bit conditional stores to
;;;					secondary address space, little-endian
;;;	STDFA(ASI_PST16_P, 0xC2)	Four 16-bit conditional stores to
;;;					primary address space
;;;	STDFA(ASI_PST16_S, 0xC3)	Four 16-bit conditional stores to
;;;					secondary address space
;;;	STDFA(ASI_PST16_PL, 0xCA)	Four 16-bit conditional stores to
;;;					primary address space, little-endian
;;;	STDFA(ASI_PST16_SL, 0xCB)	Four 16-bit conditional stores to
;;;					secondary address space, little-endian
;;;	STDFA(ASI_PST32_P, 0xC4)	Two 32-bit conditional stores to
;;;					primary address space
;;;	STDFA(ASI_PST32_S, 0xC5)	Two 32-bit conditional stores to
;;;					secondary address space
;;;	STDFA(ASI_PST832_PL, 0xCC)	Two 32-bit conditional stores to
;;;					primary address space, little-endian
;;;	STDFA(ASI_PST32_SL, 0xCD)	Two 32-bit conditional stores to
;;;					secondary address space, little-endian
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Partial Store Instructions ==
;; stda freg, [reg] reg, imm_asi
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;; Short Floating-Point Load and Store Instructions
;;;
;;; LDDFA(ASI_FL8_P, 0xD0)	8-bit load/store from/to primary address space
;;; STDFA(ASI_FL8_P, 0xD0)	8-bit load/store from/to primary address space
;;;
;;; LDDFA(ASI_FL8_S, 0xD1)	8-bit load/store from/to secondary address
;;; STDFA(ASI_FL8_S, 0xD1)	space
;;;
;;; LDDFA(ASI_FL8_PL, 0xD8)	8-bit load/store from/to primary address
;;; STDFA(ASI_FL8_PL, 0xD8)	space, little-endian
;;;
;;; LDDFA(ASI_FL8_SL, 0xD9)	8-bit load/store from/to secondary address
;;; STDFA(ASI_FL8_SL, 0xD9)	space, little-endian
;;;
;;; LDDFA(ASI_FL16_P, 0xD2)	16-bit load/store from/to primary address space
;;; STDFA(ASI_FL16_P, 0xD2)
;;;
;;; LDDFA(ASI_FL16_S, 0xD3)	16-bit load/store from/to secondary address
;;; STDFA(ASI_FL16_S, 0xD3)	space
;;;
;;; LDDFA(ASI_FL16_PL, 0xDA)	16-bit load/store from/to primary address
;;; STDFA(ASI_FL16_PL, 0xDA)	space, little-endian
;;;
;;; LDDFA(ASI_FL16_SL, 0xDB)	16-bit load/store from/to secondary address
;;; STDFA(ASI_FL16_SL, 0xDB)	space, little-endian
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Short Floating-Point Load Instructions ==
;; ldda [reg_addr] imm_asi, freg 
;; ldda [reg_plus_imm] %asi, freg
;; *** Alternate Address Spaceは未サポート ***

;; == Short Floating-Point Store Instructions ==
;; stda freg, [reg_addr] imm_asi
;; stda freg, [reg_plus_imm] %asi
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;; Block Load and Store Instructions
;;;
;;; LDDFA(ASI_BLK_AIUP, 0x70)	64-byte block load/store from/ to primary
;;; STDFA(ASI_BLK_AIUP, 0x70)	address space, user privilege
;;;
;;; LDDFA(ASI_BLK_AIUS, 0x71)	64-byte block load/store from/ to secondary
;;; STDFA(ASI_BLK_AIUS, 0x71)	address space, user privilege
;;;
;;; LDDFA(ASI_BLK_AIUPL, 0x78)	64-byte block load/store from/ to primary
;;; STDFA(ASI_BLK_AIUPL, 0x78)	address space, user privilege, little-endian
;;;
;;; LDDFA(ASI_BLK_AIUSL, 0x79)	64-byte block load/store from/ to secondary
;;; STDFA(ASI_BLK_AIUSL, 0x79)	address space, user privilege, little-endian
;;;
;;; LDDFA(ASI_BLK_P, 0xF0)	64-byte block load/store from/to primary
;;; STDFA(ASI_BLK_P, 0xF0)	address space
;;;
;;; LDDFA(ASI_BLK_S, 0xF1)	64-byte block load/store from/ to secondary
;;; STDFA(ASI_BLK_S, 0xF1)	address space
;;;
;;; LDDFA(ASI_BLK_PL, 0xF8)	64-byte block load/store from/to primary
;;; STDFA(ASI_BLK_PL, 0xF8)	address space, little-endian
;;;
;;; LDDFA(ASI_BLK_SL, 0xF9)	64-byte block load/store from/to secondary
;;; STDFA(ASI_BLK_SL, 0xF9)	address space, little-endian
;;;
;;; STDFA(ASI_BLK_COMMIT_P, 0xE0)	64-byte block commit store to primary
;;;					address space
;;; STDFA(ASI_BLK_COMMIT_S, 0xE1)	64-byte block commit store to secondary
;;;					address space
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Block Load Instructions ==
;; ldda [reg_addr] imm_asi, freg
;; ldda [reg_plus_imm] %asi, freg
;; *** Alternate Address Spaceは未サポート ***

;; == Block Store Instructions ==
;; stda freg, [reg_addr] imm_asi
;; stda freg, [reg_plus_imm] %asi
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;; Atomic Quad Load
;;;
;;;	LDDA(ASI_NUCLEUS_QUAD_LDD, 0x24)	128-bit atomic load
;;;	LDDA(ASI_NUCLEUS_QUAD_LDD_L, 0x2C)	128-bit atomic load, little
;;;						endian
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == Atomic Quad Load ==
;; ldda [reg_addr] imm_asi, reg
;; ldda [reg_plus_imm] %asi, reg
;; *** Alternate Address Spaceは未サポート ***


;;;----------------------------------------------------------------------
;;; SHUTDOWN
;;;
;;;	SHUTDOWN	Shutdown to enter power down mode
;;;
;;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

;; == SHUTDOWN ==
;; shutdown
;; *** Power Managementは未サポート ***